Semiconductor memory device and methods thereof

1. A semiconductor memory device, comprising: an internal address generating circuit operating in accordance with a first addressing protocol during normal operation and operating in accordance with a second addressing protocol during a test operation, the first addressing protocol associated with a first number of clock cycles for transferring a memory address and the second addressing protocol associated with a second number of clock cycles for transferring a memory address, the first number of clock cycles being greater than the second number of clock cycles wherein, during the test operation, a first external address is received during first and second clock cycles of a clock signal, and the internal address generating circuit outputs a first internal address and a first internal command in a third clock cycle of the clock signal, the first internal address and the first internal command respectively corresponding to the first external address and a first external command, a second external address is consecutively received after the first external address and a second external command is received two clock cycles from that of the first external command, wherein an interval between the first internal command and a second internal command corresponding to the second external command is equal to a single clock cycle.

2. The semiconductor memory device of claim 1 , wherein the first addressing protocol is a double pumped address (DPA) protocol and the second addressing protocol is a single pumped address (SPA) protocol, the DPA protocol allowing memory address transfers during two clock cycles and the SPA protocol allowing memory address transfers during a single clock cycle.

3. The semiconductor memory device of claim 1 , wherein the internal address generating circuit includes: first and second flip-flips for receiving the first and second external addresses, the first and second flip-flips operating in response to the clock signal; third, fourth and fifth flip-flops for receiving the first and second external commands and generating the first and second internal commands in response to the clock signal; first and second latches for latching output signals of the first and second flip-flops, respectively, and outputting a second internal address corresponding to the second external address; third and fourth latches for latching output signals of the first and second latches, respectively, and outputting the first internal address; and a single pumped address (SPA) mode start operating unit for receiving the clock signal, an output signal of the fifth flip-flop and an SPA mode signal, and performing a logical operation so as to delay the first internal address by one clock cycle.

4. The semiconductor memory device of claim 3 , wherein the internal address generating circuit further includes: first and second transmission gates positioned in front of the first and second latches, respectively, the first and second transmission gates selectively turned on or off based on an output signal of the fourth flip-flop, to selectively apply output signals of the first and second flip-flops to the first and second latches.

5. The semiconductor memory device of claim 4 , wherein the internal address generating circuit further includes: third and fourth transmission gates positioned in front of the third and fourth latches, respectively, the third and fourth transmission gates selectively turned on or off based on an output signal of the SPA mode start operating unit, to selectively apply output signals of the first and second latches to the third and fourth latches.

6. The semiconductor memory device of claim 5 , wherein each of the third and fourth transmission gates include: an n-type Metal Oxide Semiconductor (NMOS) transistor including a gate receiving the output signal of the SPA mode start operating unit; and a p-type Metal Oxide Semiconductor (PMOS) transistor including a gate receiving an inverted version of the output signal of the SPA mode start operating unit.

7. The semiconductor memory device of claim 5 , wherein the SPA mode start operating unit includes: a first NAND gate performing a NAND operation on the clock signal and the output signal of the fifth flip-flop to output a first NAND result; and a second NAND gate performing a NAND operation on the first NAND result and the SPA mode signal, and outputting a second NAND result to the third and fourth transmission gates.

8. The semiconductor memory device of claim 1 , wherein the internal address generating circuit outputs a second internal address and a second internal command respectively corresponding to the second external address and the second external command in a fourth clock cycle of the clock signal, the first external command is received during the first clock cycle of the clock signal, and the second external address and the second external command are received during the third and fourth clock cycles of the clock signal.

9. The semiconductor memory device of claim 8 , wherein the internal address generating circuit comprises: first and second flip-flips for receiving the first and second external addresses, the first and second flip-flips operating in response to the clock signal; third, fourth and fifth flip-flops for receiving the first and second external commands, and generating the first and second internal commands in response to the clock signal; first and second latches for latching output signals of the first and second flip-flops, respectively, and outputting the second internal address; first and second transmission gates positioned in front of the first and second latches, respectively, the first and second transmission gates selectively turned on or off based on an output signal of the fourth flip-flop, to selectively apply output signals of the first and second flip-flops to the first and second latches; third and fourth latches for latching output signals of the first and second latches, and outputting the first internal address; an SPA mode start operating unit for receiving the clock signal, an output signal of the fifth flip-flop and an SPA mode signal, and performing a logical operation so as to delay the first internal address by one clock cycle; and third and fourth transmission gates positioned in front of the third and fourth latches, respectively, the third and fourth transmission gates selectively turned on or off based on an output signal of the SPA mode start operating unit, to selectively apply output signals of the first and second latches to the third and fourth latches.

10. The semiconductor memory device of claim 9 , wherein the first external address is divided into a first lower address and a first higher address so as to correspond to the first and second clock cycles, respectively, of the clock signal, and the second external address is divided into a second lower address and a second higher address so as to correspond to the third and fourth clock cycles, respectively, of the clock signal.

11. The semiconductor memory device of claim 10 , wherein the first flip-flop outputs the first lower address in response to the first clock cycle of the clock signal, the first higher address in response to the second clock cycle of the clock signal, the second lower address in response to the third clock cycle of the clock signal, and the second higher address in response to the fourth clock cycle of the clock signal.

12. The semiconductor memory device of claim 11 , wherein the second flip-flop receives the output signal of the first flip-flop, and outputs the first lower address in response to the second clock cycle of the clock signal, and the second lower address in response to the fourth clock cycle of the clock signal.

13. The semiconductor memory device of claim 9 , wherein the third flip-flop receives the first external command, and outputs the first internal command to the fourth flip-flop in response to the first clock cycle of the clock signal, and receives the second external command, and outputs the second internal command to the fourth flip-flop in response to the third clock cycle of the clock signal.

14. The semiconductor memory device of claim 9 , wherein the fourth flip-flop receives the first internal command output from the third flip-flop, and outputs the first internal command to the fifth flip-flop, the first transmission gate and the second transmission gate in response to the second clock cycle of the clock signal, and receives the second internal command output from the third flip-flop, and outputs the second internal command to the fifth flip-flop, the first transmission gate and the second transmission gate in response to the fourth clock cycle of the clock signal.

15. The semiconductor memory device of claim 9 , wherein the fifth flip-flop receives the first internal command output from the fourth flip-flop, and outputs the first internal command to the SPA mode start operating unit in response to the third clock cycle of the clock signal.

16. The semiconductor memory device of claim 9 , wherein the first and second transmission gates are controlled and selectively turned on or off based on the first internal command output from the fourth flip-flop in response to the second clock cycle of the clock signal and by the second internal command output from the fourth flip-flop in response to the fourth clock cycle of the clock signal.

17. The semiconductor memory device of claim 9 , wherein the third and fourth transmission gates are turned on if an output signal of the SPA mode start operating unit is set to a first logic level, and are turned on if the SPA mode start signal is set to a second logic level.

18. The semiconductor memory device of claim 17 , wherein the SPA mode start operating unit outputs the first logic level if the semiconductor memory device is not performed the test operation.

19. The semiconductor memory device of claim 17 , wherein the SPA mode start operating unit outputs the second logic level in the second clock cycle of the clock signal, and output the first logic level in the third clock cycle of the clock signal during the test operation.

20. The semiconductor memory device of claim 8 , wherein the first external command is an active command, and the second external command is one of a read command and a write command.

21. A method of operating a semiconductor memory device, comprising: operating an internal address generating circuit in accordance with a first addressing protocol during normal operation; and operating the internal address generating circuit in accordance with a second addressing protocol during a test operation, the first addressing protocol associated with a first number of clock cycles for transferring a memory address and the second addressing protocol associated with a second number of clock cycles for transferring a memory address, the first number of clock cycles being greater than the second number of clock cycles, wherein operating the internal address generating circuit during the test operation includes receiving a first external address during first and second clock cycles of a clock signal, outputting, by the internal address generating circuit, a first internal address and a first internal command in a third clock cycle of the clock signal, the first internal address and the first internal command respectively corresponding to the received first external address and a first external command, consecutively receiving a second external address after the first external address, and receiving a second external command two clock cycles from that of the first external command, an interval between the first internal command and a second internal command corresponding to the received second external command being equal to a single clock cycle.

22. The method of claim 21 , wherein the first addressing protocol is a double pumped address (DPA) protocol and the second addressing protocol is a single pumped address (SPA) protocol, the DPA protocol allowing memory address transfers during two clock cycles and the SPA protocol allowing memory address transfers during a single clock cycle.

23. A method for achieving an single pumped address (SPA) mode in a semiconductor memory device configured for a double pumped address (DPA) mode, comprising: receiving a first external address; generating a first internal address corresponding to the received first external address; receiving a second external address; generating a second internal address corresponding to the received second external address; and delaying the generation of the first internal address to reduce a clock cycle interval between the generated first and second internal addresses, wherein, during the SPA mode, the method further includes receiving the first external address during first and second clock cycles of a clock signal, outputting, by an internal address generating circuit, the first internal address and a first internal command in a third clock cycle of the clock signal, the first internal address and the first internal command respectively corresponding to the received first external address and a first external command, consecutively receiving the second external address after the first external address, and receiving a second external command two clock cycles from that of the first external command, an interval between the first internal command and a second internal command corresponding to the received second external command being equal to a single clock cycle.

24. The method of claim 23 , wherein the second external address is received during third and fourth clock cycles of the clock signal, and the second internal address is generated during the fourth clock cycle of the clock signal.

25. The method of claim 24 , wherein, if the delaying step is not performed, the first internal address is generated during the second clock cycle of the clock signal.