Inrush current control

1. A power supply system comprising: a variable voltage source configured to provide and incrementally increase a control voltage associated with a pass-transistor; an inrush current monitor configured to monitor a current-flow associated with the pass-transistor; and a voltage control circuit configured to temporarily halt the incremental increase of the control voltage in response to the current-flow exceeding a predetermined current limit, wherein the current-flow associated with the pass-transistor is maintained at the predetermined current limit by the control voltage on a gate capacitance of the pass-transistor until the current-flow drops below the predetermined current limit, then allowing the control voltage to again increase incrementally from a point at which its incremental increase was halted.

2. The power supply system of claim 1 , wherein the pass-transistor is configured to couple a capacitive load to a positive supply voltage to charge the capacitive load.

3. The power supply system of claim 1 , wherein the inrush current monitor comprises a second transistor coupled in series with a sense-resistor, the second transistor being matched with the pass-transistor and activated by the control voltage.

4. The power supply system of claim 3 , wherein the inrush current monitor further comprises a differential amplifier configured to monitor a first voltage associated with the sense-resistor to generate a second voltage that is associated with the current-flow associated with the pass-transistor.

5. The power supply system of claim 4 , wherein voltage control circuit comprises a comparator configured to compare the second voltage with a predetermined limit voltage that is associated with the predetermined current limit.

6. The power supply system of claim 5 , wherein the voltage control circuit further comprises an AND-gate configured to receive a clock signal and an output of the comparator and to provide a modified clock signal that is configured to control a rate of incremental increase of the control voltage provided by the variable voltage source, the AND-gate being configured to mask the clock signal in response to the second voltage being greater than the predetermined limit voltage.

7. The power supply system of claim 1 , wherein the variable voltage source is configured as a charge-pump operative to incrementally increase the control voltage based on a clock signal.

8. The power supply system of claim 1 , wherein the voltage control circuit comprises an AND-gate configured to mask a clock signal to the variable voltage source in response to a voltage associated with the current-flow being greater than a predetermined limit voltage that is associated with the predetermined current limit.

9. The power supply system of claim 8 , wherein the inrush current monitor comprises a differential amplifier configured to generate the voltage associated with current-flow based on a current-flow through a sense-resistor and second transistor configured in parallel with the pass-transistor.

10. A power converter system comprising the power supply system of claim 1 .

11. An integrated circuit comprising the power supply system of claim 1 .

12. A method for limiting inrush current associated with a pass-transistor, the method comprising: setting a predetermined limit voltage that is associated with a desired current limit of the pass-transistor; incrementally increasing a control voltage that is associated with the pass-transistor based on a clock signal to provide a current-flow associated with the pass-transistor; and temporarily masking the clock signal in response to a sense-voltage that is associated with the current-flow being greater than the predetermined limit voltage, wherein the current-flow associated with the pass-transistor is maintained at the predetermined current limit by the control voltage on a gate capacitance of the pass-transistor until the current-flow drops below the predetermined current limit, then unmasking the clock signal to allow the control voltage to again increase incrementally from a point at which the clock signal was masked.

13. The method of claim 12 , further comprising charging a capacitive load with the current-flow associated with the pass-transistor.

14. The method of claim 12 , further comprising monitoring a second current-flow through a sense-resistor that is configured in a parallel current path with the pass-transistor to generate the sense-voltage.

15. The method of claim 14 , further comprising controlling a second transistor that is configured in series with the sense-resistor via the control voltage.

16. The method of claim 12 , wherein masking the clock signal comprises: comparing the sense-voltage with the predetermined limit voltage; and setting the clock signal to substantially zero frequency via an AND-gate upon the sense-voltage being greater than the predetermined limit voltage.

17. A power supply system comprising: means for charging a capacitive load upon incrementing an enable signal; means for incrementally increasing a control voltage associated with the means for charging to provide a current-flow through the capacitive load based on a clock signal; means for monitoring a magnitude of the current-flow through the capacitive load; and means for temporarily masking the clock signal in response to the magnitude of the current-flow being greater than a predetermined current limit, wherein the current-flow associated with the pass-transistor is maintained at the predetermined current limit by the control voltage on a gate capacitance of the pass-transistor until the current-flow drops below the predetermined current limit, then unmasking the clock signal to allow the control voltage to again increase incrementally from a point at which the clock signal was masked.

18. The power supply system of claim 17 , wherein the means for monitoring comprises: means for measuring a current-flow through a sense-resistor that is configured in a current path in series with the capacitive load and for generating a sense-voltage that is associated with the current-flow through the capacitive load.

19. The power supply system of claim 18 , wherein the means for masking comprises means for comparing the sense-voltage with a predetermined limit voltage that is associated with the predetermined current limit.

20. The power supply system of claim 17 , wherein the means for masking comprises a logical operator configured to set the clock signal to substantially zero frequency in response to the magnitude of the current-flow being greater than a predetermined current limit.