Method of forming a semiconductor device using stress memorization

1. A method of forming a semiconductor device comprising: providing a semiconductor substrate; forming an n-channel transistor structure overlying and within the semiconductor substrate, wherein the n-channel transistor structure includes a gate dielectric overlying a channel region within the semiconductor substrate, a gate stack overlying the gate dielectric, a sidewall spacer adjacent a sidewall of the gate stack and overlying a portion of the semiconductor substrate proximate the channel region, and source and drain implant regions within the semiconductor substrate proximate the channel region; forming a p-channel structure overlying and within the semiconductor substrate, wherein the p-channel transistor structure includes a gate dielectric overlying a channel region within the semiconductor substrate, a gate stack overlying the gate dielectric, a sidewall spacer adjacent a sidewall of the gate stack of the p-channel transistor structure and overlying a portion of the semiconductor substrate proximate the channel region of the p-channel transistor structure, and source and drain implant regions within the semiconductor substrate proximate the channel region of the p-channel transistor structure; forming a stress memorization technique (SMT) layer over the n-channel transistor structure and the p channel structure; removing the SMT layer from over the p-channel transistor structure and leaving the SMT layer over the n-channel transistor structure; transferring a stress from the SMT layer into the channel of the n-channel transistor structure, wherein transferring the stress excludes any appreciable gate dielectric degradation; removing the SMT layer overlying the n-channel transistor structure subsequent to the stress transfer; and activating dopants of the source and drain implant regions of the n-channel transistor structure after removing the SMT layer overlying the n-channel transistor structure.

2. The method of claim 1 , wherein transferring the stress includes performing a first anneal, the first anneal comprising one of a group consisting of a millisecond type anneal, a laser anneal, and a low temperature rapid thermal anneal, wherein low temperature includes a temperature less than on the order of 1035° C.

3. The method of claim 2 , wherein the first anneal includes a laser anneal for annealing at a temperature on the order on 1200-1350 degrees Celsius (1200° C.-1350° C.).

4. The method of claim 1 , wherein activating dopant of the source and drain implant regions includes performing a second anneal.

5. The method of claim 4 , wherein: the second anneal includes a spike anneal that includes a temperature ramp up from a starting temperature to a peak temperature that is immediately followed by a ramp down from the peak temperature to a final temperature; the ramp up includes a ramp up rate on the order of two hundred degrees Celsius per second (200° C./s); and the ramp down includes a ramp down rate on the order of seventy-five degrees Celsius per second (75° C./s).

6. The method of claim 5 , wherein the starting temperature comprises on the order of room temperature and the peak temperature comprises on the order of 1065 degrees Celsius (1065° C.).

7. The method of claim 1 , wherein the steps of (i) transferring stress and (ii) activating dopant are decoupled from one another.

8. The method of claim 1 , wherein the SMT layer overlying the n-channel transistor structure experiences only a first anneal for transferring stress.

9. The method of claim 8 , wherein removal of the SMT layer prior to activating dopant of the source and drain implant regions of the n-channel transistor structure prevents the SMT layer overlying the n-channel transistor structure from being subjected to the second anneal and thereby prevents any gate dielectric degradation which could occur if the SMT layer overlying the n-channel transistor structure is subjected to the second anneal.

10. The method of claim 1 , wherein (i) stress transfer from the SMT layer into the channel of the n-channel transistor structure and (ii) subsequent dopant activation occur in the absence of gate dielectric degradation, wherein gate dielectric degradation comprises oxide growth in regions of the semiconductor substrate proximate edges of the gate dielectric.

11. The method of claim 1 , further comprising: siliciding exposed portions of the source and drain regions and the gate stack after the step of activating.

12. The method of claim 1 , wherein the gate dielectric comprises a high-k dielectric, and wherein the gate stack includes a metal layer overlying the high-k dielectric.

13. The method of claim 1 , wherein the SMT layer includes a liner having a thickness on the order of 50-150 angstroms that is formed prior to a remainder of the SMT layer having a thickness on the order of 300-800 angstroms.

14. The method of claim 13 , wherein the SMT layer comprises a plasma enhanced chemical vapor deposition (PECVD) nitride and the liner comprises an oxide.

15. The method of claim 1 , further comprising: forming a resistor within a third portion of the semiconductor substrate, wherein: forming the SMT layer further includes forming the SMT layer over the n-channel transistor structure, the p-channel transistor structure, and the resistor; the steps of removing the SMT layer are characterized as leaving the SMT layer over the resistor; and siliciding the sources and drains of the p-channel and n-channel transistor structures while the SMT layer is over the resistor so that the SMT layer prevents silicidinq the resistor.