Memory devices and methods are disclosed to facilitate utilization of a multi level inhibit programming scheme. In one such embodiment, isolated channel regions having boosted channel bias levels are formed across multiple memory cells and are created in part and maintained through capacitive coupling with word lines coupled to the memory cells and biased to predetermined bias levels. Methods of manipulation of isolated channel region bias levels through applied word line bias voltages affecting a program inhibit effect, for example, are also disclosed.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of programming memory cells of a NAND memory device each memory cell having a desired data state, comprising: biasing a first channel region to a first voltage; biasing a second channel region to a second voltage, wherein the first voltage is higher than the second voltage; applying a programming voltage to a control gate of a selected memory cell coupled to the second channel region; biasing the first channel region to a third voltage that is higher than the first voltage; biasing the second channel region to a fourth voltage that is higher than the second voltage, wherein the third voltage is higher than the fourth voltage; decreasing the voltage of the second channel region while continuing to apply the programming voltage, wherein the selected memory cell experiences an effective programming potential while a memory cell coupled to the first channel region and having a control gate coupled to the control gate of the selected memory cell is substantially inhibited from experiencing the effective programming potential; and at least partially in response to the selected memory cell approaching its desired data state, increasing the voltage of the second channel region, wherein a programming rate of the selected memory cell is thereby reduced.
2. The method of claim 1 , further comprising sharing the channel bias of each memory cell coupled to the selected word line with one or more memory cells coupled in series with that respective memory cell.
3. The method of claim 2 , further comprising isolating the channel bias of each memory cell coupled to the selected word line from one or more other memory cells coupled in series with that respective memory cell.
4. The method of claim 1 , wherein decreasing the voltage of the second channel region while continuing to apply the programming voltage to the selected memory cell comprises pulling the second channel bias to a ground potential.
5. The method of claim 1 further comprising performing an erase operation on the memory cells prior to programming the memory cells wherein the memory cells are erased to a first data state.
6. The method of claim 5 , wherein the voltage on the first channel region is decreased if the memory cell coupled to the first channel region requires programming to achieve the first data state.
7. A method of programming a selected plurality of memory cells of an array of memory cells, the selected plurality having their control gates commonly coupled and wherein each of the cells in the selected plurality is coupled to a respective one of a plurality of NAND strings each NAND string having a respective line coupled to a first end by a select gate, the method comprising: biasing each line with a plurality of seed voltages; biasing each select gate to place each gate in a conductive mode thereby coupling a respective seed voltage to a respective NAND string; applying a first pass voltage to control gates of all memory cells coupled to the NAND strings; isolating each NAND string from its respective line by placing each select gate into a non-conductive mode; applying a second pass voltage to the control gates of the array of memory cells other than those comprising the selected plurality; applying a first programming voltage to the control gates of the selected plurality; applying a third pass voltage to the control gates of the array of memory cells other than those comprising the selected plurality; and applying a second programming voltage to the control gates of the selected plurality.
8. The method of claim 7 wherein the first programming voltage is greater than the first and second Vpass voltages.
9. The method of claim 7 wherein the second programming voltage is greater than the first programming voltage and the first, second and third Vpass voltages.
10. The method of claim 7 wherein applying a voltage comprises ramping up a voltage from a previously applied voltage.
11. The method of claim 7 wherein the first Vpass voltage is substantially equal to 3V, the second Vpass voltage is substantially equal to 6V and the third Vpass potential is substantially equal to 9V.
12. The method of claim 7 wherein the first programming voltage is substantially equal to 11V and the second programming voltage is substantially equal to 24V.
13. The method of claim 7 further comprising charging a NAND string with the seed voltage present on its respective line prior to isolating the NAND string from the drain line.
14. The method of claim 7 wherein the plurality of seed voltages range from substantially 0V to 2.5V.
15. The method of claim 7 wherein the seed voltage biasing a line is selected based on the amount of threshold voltage shift required to program a memory cell coupled to the line.
16. The method of claim 7 further comprising isolating a portion of memory cells comprising a selected memory cell from a source line coupled to a second end of each NAND string by biasing an unselected memory cell interposed between the selected memory cell and the source line with a ground potential.
17. A memory device, comprising: a plurality of memory cells serially coupled source to drain in a NAND string configuration; a drain select gate coupled to a drain line and a first end of the NAND string of memory cells; a source select gate coupled to a source line and a second end of the NAND string of memory cells; a plurality of word lines wherein a single word line is coupled to a single memory cell of the plurality of memory cells; and control circuitry configured to perform a program operation on a selected memory cell, wherein the control circuitry is further configured to: bias the drain line with a seed voltage; bias the drain select gate into a conductive or non-conductive mode; apply a first Vpass bias voltage to the plurality of word lines coupled to the NAND string of memory cells; apply a second Vpass bias voltage to the plurality of word lines except a word line coupled to the selected memory cell; apply a first programming voltage to the word line coupled to the selected memory cell; isolate the NAND string from the drain line by biasing the drain select gate into a non-conductive mode; apply a third Vpass bias voltage to the plurality of word lines except the word line coupled to the selected memory cell; and apply a second programming voltage to the word line coupled to the selected memory cell.
18. The memory device of claim 17 wherein the control circuitry is further configured to isolate a subset string of memory cells from the source line wherein the subset string comprises the selected memory cell.
19. The memory device of claim 18 wherein the control circuitry is further configured to apply a ground potential to a word line which is interposed between the word line coupled to the selected memory cell and the source select gate.
20. The memory device of claim 17 wherein the seed voltage comprises a voltage substantially in the range of 0V to 2.5V.
21. A flash memory device, comprising: a NAND configured string of memory cells, wherein the NAND string comprises a plurality of memory cells serially coupled source to drain, a drain select gate coupled to a drain line and a first end of the NAND string, a source select gate coupled to a source line and a second end of the NAND string and a plurality of word lines wherein a single word line is coupled to a single memory cell of the plurality of memory cells; and control circuitry configured to perform a program operation on a selected memory cell, wherein the control circuitry is further configured to: bias the drain line with a seed voltage; bias the drain select gate into a conductive or non-conductive mode; apply a first Vpass bias voltage to the plurality of word lines coupled to the NAND string; apply a second Vpass bias voltage to the plurality of word lines except a word line coupled to the selected memory cell; apply a first programming voltage to the word line coupled to the selected memory cell; create a substring of memory cells from the NAND string wherein the substring is isolated from the source line and the selected memory cell comprises one of the memory cells of the substring; isolate the substring from the drain line by biasing the drain select gate into a non-conductive mode; apply a third Vpass bias voltage to the plurality of word lines coupled to memory cells of the substring except the word line coupled to the selected memory cell; and apply a second programming voltage to the word line coupled to the selected memory cell.
22. The memory device of claim 21 further comprising a register configured to store a programming status of the selected memory cell wherein the programming status indicates if the selected memory cell requires additional programming.
23. The memory device of claim 21 wherein the second Vpass bias voltage and the first programming voltage are applied substantially simultaneously and the third Vpass bias voltage and the second programming voltage are applied substantially simultaneously.
24. The memory device of claim 21 wherein the control circuitry is further configured to isolate the substring from the source line by biasing a word line of a non-selected memory cell interposed between the substring and the source line with a bias voltage sufficient to render the non-selected memory cell non-conductive.
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March 31, 2008
January 4, 2011
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