A semiconductor memory device includes a first buffering unit configured to buffer a first clock for an address signal and a command to be input in synchronization with the first clock, a second buffering unit configured to buffer a second clock for a data signal to be in synchronization with the second clock to output a buffered second clock having the same frequency as the first clock, a data output circuit configured to output an internal data in response to the buffered second clock, a delay unit configured to delay the buffered second clock by a predetermined time, and a phase detector configured to detect a phase difference of an output clock of the delay unit and the output clock of the first buffering unit, and to output the detection result.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor memory device, comprising: a first pad configured to receive a system clock for an address signal and a command to be input in synchronization with the system clock; a second pad configured to receive a data clock having a higher frequency than the system clock for a data signal to be in synchronization with the data clock; a first buffering unit configured to buffer the system clock; a second buffering unit configured to buffer the data clock and divide the buffered clock to have the same frequency as the system clock; a data output circuit configured to output the data signal in response to an output clock of the second buffering unit; and a phase detector configured to detect a phase difference between an output clock of the first buffering unit and the output clock of the second buffering unit, and to output the detection result to an external controller, wherein the system clock and the data clock are separately input from the external controller.
2. The semiconductor memory device as recited in claim 1 , wherein a phase of the data clock is changed according to the detection result of the phase detector.
3. The semiconductor memory device as recited in claim 1 , wherein the second buffering unit includes: a clock buffer unit configured to buffer the data clock; and a frequency dividing unit configured to divide a frequency of an output clock of the clock buffer unit.
4. The semiconductor memory device as recited in claim 1 , wherein the data output circuit includes: a latch unit configured to align the data signal on the basis of the output clock of the second buffer; and a data output driver unit configured to drive an output data of the latch unit to a predetermined data input/output pad.
5. A method for operating a semiconductor memory device, the method comprising: receiving a system clock from an external controller for an address signal and a command to be input in synchronization with the system clock; receiving a data clock from the external controller—having a higher frequency than the system clock for a data signal to be in synchronization with the data clock; buffering the system clock for a predetermined first time to output a buffered system clock; buffering the data clock and dividing the buffered clock for a predetermined second time to have the same frequency as the system clock, to output a buffered data clock; outputting the data signal in response to the buffered data clock for a predetermined third time; and detecting a phase difference between the buffered system clock and the buffered data clock to output the detection result, wherein the system clock and the data clock are separately inputted from the external controller.
6. The method as recited in claim 5 , further comprising changing a phase of the data clock according to the detection result.
7. The method as recited in claim 5 , wherein the outputting of the data signal includes: aligning the data signal on the basis of the buffered data clock; and driving the aligned data signal to a predetermined data input/output pad.
8. A semiconductor memory device, comprising: a first buffering unit configured to buffer a system clock from the external controller for an address signal and a command to be input in synchronization with the system clock; a second buffering unit configured to buffer a data clock from the external controller for a data signal to be in synchronization with the data clock to output a buffered data clock having the same frequency as the system clock; a data output circuit configured to output a data signal in response to the buffered data clock; and a phase detector configured to detect a phase difference between the buffered system clock and the buffered data clock and to output the detection result.
9. The semiconductor memory device as recited in claim 1 , further comprising: a delay unit configured to delay the output clock of the second buffering unit by a predetermined time.
10. The semiconductor memory device as recited in claim 9 , wherein the phase detector detects a phase difference of an output clock of the delay unit and the output clock of the first buffering unit, and outputs the detection result.
11. The semiconductor memory device as recited in claim 8 , further comprising: a delay unit configured to delay the buffered data clock by a delay time caused by the first buffering unit and the data output circuit.
12. The semiconductor memory device as recited in claim 11 , wherein the phase detector detects a phase difference between an output clock of the delay unit and the output clock of the first buffering unit, and outputs the detection result.
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May 28, 2008
January 4, 2011
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