Spacer electrode small pin phase change RAM and manufacturing method

1. A method for manufacturing a memory device, comprising: forming an electrode layer having a top surface, the electrode layer including a first pan-shaped electrode and a second pan-shaped electrode, and an insulating wall between the first and second pan-shaped electrodes, and wherein the first and second pan-shaped electrodes have respective first and second side wall structures, and the insulating wall and the respective first and second side wall structures extend to the top surface of the electrode layer, and the insulating wall has a width between the first and second side wall structures at the top surface; forming a bridge of memory material on the top surface of the electrode layer across the insulating wall, the bridge comprising a patch of memory material having a first side and a second side and contacting the first and second side wall structures on the first side, the bridge defining an inter-electrode path between the first and second side wall structures across the insulating wall having a path length defined by the width of the insulating wall, wherein the memory material comprises a programmable resistive material.

2. The method of claim 1 , wherein the first pan-shaped electrode and second pan-shaped electrode respectively comprise a pad member in electrical communication with the respective first and second sidewall structures and having a thickness less than the height of the respective first and second sidewall structures extending generally away from the insulating wall.

3. The method of claim 1 , wherein the insulating walls are formed by patterning a layer of resist material using a lithographic process to define trenches in the dielectric layer, with patches positioned to define narrow walls between the trenches; then trimming the width of the patches to define a more narrow patches of the resist material; and using the more narrow patches of the resist material as an etch mask to form the insulating walls.

4. The method of claim 1 , wherein the insulating walls are formed by patterning a layer of resist material using a lithographic process to define trenches in the dielectric layer, with patches positioned to define narrow walls between the trenches; etching the dielectric layer using the patterned layer of resist material; and isotropically etching the narrow walls.

5. The method of claim 1 , wherein the widths of the first and second side wall structures at the top sides are sufficient to provide electrical contacts to the bridge and less than about 50 nm.

6. The method of claim 1 , wherein the widths of the insulating walls are about 50 nm or less, and said bridge comprises a thin film with a thickness about 50 nm or less and a width about 50 nm or less, and wherein the widths of the first and second electrodes at the top sides are sufficient to provide electrical contacts to the bridge and less than about 50 nm.

7. The method of claim 1 , wherein the width of the insulating wall is about 40 nm or less, and said bridge comprises a thin film with a thickness about 20 nm or less and a width about 50 nm or less.

8. The method of claim 1 , wherein said bridge comprises a thin film with a thickness about 20 nm or less and a width about 50 nm or less.

9. The method of claim 1 , wherein the electrode layer is made by a process comprising: forming a dielectric layer on a substrate: etching the dielectric layer to form insulating walls: forming a conductive layer over the dielectric layer; and depositing a fill material over the conductive layer and polishing fill material and the conductive layer to define a top surface of the electrode layer and to form pairs of pan-shaped electrode members including sidewall conductor structures abutting respective sides of the insulating walls, wherein the pairs of sidewall conductor structures and insulating walls are exposed on the top surface and act as the first electrode, the second electrode and the insulating wall, respectively.

10. A method for manufacturing a memory device, comprising: forming circuitry in a substrate having a top surface, the circuitry including an array of contacts on the top surface of the substrate; forming an electrode layer on the substrate, including forming a layer of insulating material on the top surface of the substrate, defining a plurality of trenches having a depth in the layer of insulating material, the pattern of trenches including pairs of trenches separated by respective walls of insulating material having wall thicknesses, and wherein at least one trench in each of said pairs of trenches exposes a contact in the array of contacts, depositing a conformal layer of electrode material over the plurality of trenches having a thickness less than the depth of the trenches to form electrode material covered trenches, filling the electrode material covered trenches with insulating material to form a filled structure, and etching back the filled structure to expose the walls of insulating material and electrode material on the walls and to form a top surface of the electrode layer, wherein the electrode material on both sides of the walls define an array of pan-shaped electrode pairs including respective first and second pan-shaped electrodes; forming an array of bridges of memory material on the top surface of the electrode layer, the array of bridges including bridges for each of the electrode pairs in the array of electrode pairs, contacting the respective first and second side wall structures on the first and second pan-shaped electrodes and extending across the respective walls of insulating material, the bridges comprising films of memory material having a first side and a second side and contacting the respective first and second side wall structures on the first side, the bridges defining inter-electrode paths between the first and second side wall structures across the walls of insulating material having path lengths defined by the thicknesses of the walls, wherein the memory material comprises a programmable resistive material; and forming a patterned conductive layer over said bridge, and forming an array of contacts between said first electrodes in the array of electrode pairs and said patterned conductive layer.

11. The method of claim 10 , wherein the first pan-shaped electrode and second pan-shaped electrode respectively comprise a pad member in electrical communication with the respective first and second sidewall structures and having a thickness less than the height of the respective first and second sidewall structures extending generally away from the insulating wall.

12. The method of claim 10 , wherein said circuitry includes a plurality of wordlines and isolation devices controlled by signals on the plurality of wordlines, and said patterned conductive layer comprises a plurality of bit lines.

13. The method of claim 10 , wherein two electrode pairs in said array of pan-shaped electrode pairs comprise conductive members arranged in a row, including a first conductive member acting as a second pan-shaped electrode in a first of the two electrodes in a pair, a second conductive member acting as first pan-shaped electrodes in both of the two pan-shaped electrodes in a pair, and a third conductive member acting as a second pan-shaped electrode in a second of the two electrodes in a pair.

14. The method of claim 10 , wherein the memory material comprises a combination of Ge, Sb, and Te.

15. The method of claim 10 , wherein the memory material comprises a combination of two or more materials from the group of Ge, Sb, Te, Se, In, Ti, Ga, Bi, Sn, Cu, Pd, Pb, Ag, S, and Au.

16. The method of claim 10 , including isotropically etching the respective walls of insulating material.

17. The method of claim 10 , wherein defining the plurality of trenches includes forming a pattern of etch mask material, trimming the pattern by isotropic etching, and etching the layer of insulating material using the trimmed pattern.