A method for forming a depletion-mode single-poly electrically erasable programmable read-only memory (EEPROM) cell is provided. The method includes providing a substrate having a floating region and a control region. Then, an isolation deep well and a deep well are formed in the floating region and the control region of the substrate respectively. A well region is formed in the isolation deep well simultaneously with forming an isolation well region between the isolation deep well and the deep well in the substrate. A depletion doped region and a cell implant region are formed at the well region of the substrate and the deep well of the substrate respectively. A floating gate structure is formed across over the floating region and the control region. An implantation process is performed to form a source/drain region and a heavily doped region in the depletion doped region and the cell implant region respectively.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A depletion-mode single-poly EEPROM cell on a substrate, wherein the substrate has a floating region and a control region, the depletion-mode single-poly EEPROM cell comprising: an isolation deep well located in the floating region of the substrate; a deep well located in the control region of the substrate; a well region located in the isolation deep well, wherein the deep well is deeper than the well region, and a depth of the deep well is similar to a depth of the isolation deep well; a floating gate comprising a first portion and a second portion, wherein the first portion is located in the floating region and the second portion is located in the control region and-the first portion and the second portion are electrically connected; source/drain regions, one source/drain region located at each side of the floating gate in the well region of the substrate and aligned with the floating gate; a heavily doped region located at one side of the floating gate in the deep well of the substrate exposed by the floating gate, and being next to and directly contacting an isolation structure in the substrate; a depletion doped region located under a tunneling dielectric layer and extending from one of the source/drain regions to another of the source/drain regions continuously, wherein the depletion doped region has a conductivity type the same as that of the source/drain regions; and a cell implant region located under a gate dielectric layer, adjacent to the heavily doped region of the substrate and directly contacting the deep well.
2. The depletion-mode single-poly EEPROM cell of claim 1 , wherein the conductivity type of the isolation deep well is the same as that of the depletion doped region and that of the source/drain regions, and different from that of the well region.
3. The depletion-mode single-poly EEPROM cell of claim 2 , wherein the conductivity type of the heavily doped region is the same as that of the source/drain regions.
4. The depletion-mode single-poly EEPROM cell of claim 3 , wherein the depletion doped region is directly connected to the source/drain regions.
5. The depletion-mode single-poly EEPROM cell of claim 3 , wherein an ion implantation concentration of the source/drain regions is larger than that of the depletion doped region.
6. The depletion-mode single-poly EEPROM cell of claim 3 , wherein an ion implantation concentration of the heavily doped region is larger than that of the cell implant region.
7. The depletion-mode single-poly EEPROM cell of claim 1 , wherein the conductivity type of the heavily doped region is the same as that of the cell implant region and that of the deep well.
8. The depletion-mode single-poly EEPROM cell of claim 1 , wherein the tunneling dielectric layer is located between the floating gate and the well region.
9. The depletion-mode single-poly EEPROM cell of claim 8 , wherein the thickness of the tunneling dielectric layer is about 80˜120 angstroms.
10. The depletion-mode single-poly EEPROM cell of claim 1 , wherein the gate dielectric layer is located between the floating gate and the deep well.
11. The depletion-mode single-poly EEPROM cell of claim 10 , wherein the thickness of the gate dielectric layer is about 100˜1000 angstroms.
12. The depletion-mode single-poly EEPROM cell of claim 1 , wherein the floating region and the control region are located in a high voltage device region of the substrate.
13. The depletion-mode single-poly EEPROM cell of claim 1 , wherein the heavily doped region is located only at one side of the floating gate.
14. The depletion-mode single-poly EEPROM cell of claim 13 , wherein the isolation structure is further located at the other side of the floating gate and the cell implant region is directly connected to the isolation structure and the heavily doped region.
15. The depletion-mode single-poly EEPROM cell of claim 14 , wherein the depletion doped region is directly connected to the source/drain regions.
16. The depletion-mode single-poly EEPROM cell of claim 1 , wherein the tunneling dielectric layer is thinner than the gate dielectric layer.
17. The depletion-mode single-poly EEPROM cell of claim 1 , wherein the depletion doped region is directly connected to the source/drain regions.
18. The depletion-mode single-poly EEPROM cell of claim 1 , wherein the tunneling dielectric layer is separated from the well region by the depletion doped region.
19. The depletion-mode single-poly EEPROM cell of claim 1 , wherein the source/drain regions contacts the well region.
20. The depletion-mode single-poly EEPROM cell of claim 1 , wherein the heavily doped region contacts the deep well.
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July 10, 2006
January 11, 2011
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