A semiconductor substrate includes a substrate layer and a circuit film formed over the substrate layer. One or more openings are formed in the circuit film and the substrate layer. Conductive plates are formed over the circuit film at the peripheries of the openings. A semiconductor die is attached to the circuit film, below the openings with an adhesive material. A conductive material is disposed in the openings to electrically connect the semiconductor die to the conductive plates.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor substrate, comprising: a substrate layer having first and second major surfaces and a center cavity disposed in the second major surface; a circuit film deposited over the first major surface of the substrate layer, wherein the circuit film has a first surface and wherein one or more openings are formed through the first surface of the circuit film and the substrate layer at the center cavity; one or more conductive plates disposed over the first surface of the circuit film at peripheries of the openings; one or more metallic contacts formed through the first surface of the circuit film and the substrate layer; one or more conductive tracks formed on the first surface of the circuit film, wherein the conductive tracks connect the conductive plates with the metallic contacts; and an adhesive material disposed on the second major surface of the substrate layer and within the center cavity, the adhesive material for attaching a semiconductor die to the circuit film, wherein bond pads on the die are aligned with the openings for providing electrical connection of the bond pads with the conductive plates.
2. The semiconductor substrate of claim 1 , wherein the adhesive material comprises a die attach film.
3. The semiconductor substrate of claim 1 , wherein the substrate layer comprises at least one of a ceramic material and a plastic material.
4. A semiconductor package, comprising: a substrate layer having first and second major surfaces and a center cavity disposed in the second major surface; a circuit film deposited over the first major surface of the substrate layer, wherein one or more openings are formed through the circuit film and the substrate layer at the center cavity; one or more conductive plates disposed over a first surface of the circuit film at peripheries of the openings; a conductive material disposed in the openings and in contact with the conductive plates; an adhesive material deposited on the second major surface of the substrate and within the center cavity; and a semiconductor die attached to the second major surface of the substrate at the center cavity with the adhesive material, wherein one or more bond pads of the semiconductor die are aligned with the openings, and wherein the conductive material disposed in the openings electrically connects the bond pads with the conductive plates.
5. The semiconductor package of claim 4 , wherein the substrate layer further comprises one or more metallic contacts formed through the first surface of the circuit film and the substrate layer.
6. The semiconductor package of claim 5 , further comprising one or more conductive tracks formed on the first surface of the circuit film, wherein the conductive tracks electrically connect the conductive plates with the metallic contacts.
7. The semiconductor package of claim 6 , wherein at least one of the conductive plates, the metallic contacts and the conductive tracks comprises copper.
8. The semiconductor package of claim 5 , further comprising a plurality of solder bumps respectively formed over each of the metallic contacts on the substrate layer.
9. The semiconductor package of claim 4 , further comprising a die pad located between the semiconductor die and the substrate layer and below the openings.
10. The semiconductor package of claim 4 , wherein the adhesive material comprises a die attach film.
11. The semiconductor package of claim 4 , wherein the substrate layer comprises at least one of a ceramic and a plastic material.
12. The semiconductor package of claim 4 , wherein the semiconductor package includes a heat spreader.
13. The semiconductor package of claim 12 , further comprising a first thermal filler disposed between the heat spreader and the semiconductor die.
14. The semiconductor package of claim 12 , further comprising a second thermal filler disposed between the heat spreader and the first surface of the circuit film.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 25, 2009
January 11, 2011
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