Multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same

1. A thin film integrated circuit, comprising: a ceramic substrate; a glass dielectric buffer layer that overlies the ceramic substrate and has a surface polished to an Ra roughness less than or equal to 0.08 microns and substantially free of surface micropores, and is configured to withstand multiple anneals at high temperature in an oxidizing atmosphere without substantially affecting its surface quality; a thin film multi-level capacitor (MLC) that is fabricated on the buffer layer surface and that includes at least one high permittivity dielectric layer between at least two electrode layers, the electrode layers being formed from a conductive thin film material; and a high density interconnect (HDI) layer between the ceramic substrate and the buffer layer.

2. The thin film integrated circuit of claim 1 , wherein the buffer layer comprises a thick film dielectric material, whereby the thin film dielectric material contributes to the stability of the buffer layer at high temperatures.

3. The thin film integrated circuit of claim 1 further comprising: one or more additional passive thin film devices coupled to the MLC.

4. The thin film integrated circuit of claim 3 , wherein the one or more additional passive thin film devices include a thin film resistor.

5. The thin film integrated circuit of claim 3 , wherein the one or more additional passive thin film devices include a nitride capacitor.

6. The thin film integrated circuit of claim 1 , wherein the surface roughness (Ra) of the buffer layer is less than or equal to 0.06 micrometers (um).

7. The thin film integrated circuit of claim 1 , wherein the surface roughness (Ra) of the buffer layer is less than or equal to 0.03 micrometers (um).

8. The thin film integrated circuit of claim 1 , wherein the MLC has an overall capacitance density of about 10 fF/um 2 to about 390 fF/um 2 .

9. The thin film integrated circuit of claim 1 , wherein the ceramic substrate includes through holes filled with conductive material and wherein a surface of the ceramic substrate is completely covered by the glass dielectric material.

10. The thin film integrated circuit of claim 1 , wherein the ceramic substrate includes through holes filled with conductive material and wherein a surface of the ceramic substrate is partially covered by the glass dielectric material, leaving the through holes uncovered.

11. The thin film integrated circuit of claim 1 , wherein the HDI layer includes at least one routing layer and at least one layer of a thick film dielectric material.

12. The thin film integrated circuit of claim 1 , wherein the HDI layer includes one or more metal filled vias to electrically connect the MLC to metal filled through holes in the ceramic substrate.

13. The thin film integrated circuit of claim 1 , wherein the HDI layer includes one or more buried passive circuit components.

14. The thin film integrated circuit of claim 1 , wherein the thin film integrated circuit is attached to an integrated circuit chip to form a system-on-a-package (SoP) structure.

15. A thin film integrated circuit, comprising: a ceramic substrate; a glass dielectric buffer layer that overlies the ceramic substrate and has a surface polished to an Ra roughness less than or equal to 0.08 microns and substantially free of surface micropores, and is configured to withstand multiple anneals at high temperature in an oxidizing atmosphere without substantially affecting its surface quality; a thin film multi-level capacitor (MLC) that is fabricated on the buffer layer surface and that includes at least one high permittivity dielectric layer between at least two electrode layers, the electrode layers being formed from a conductive thin film material; and a high density interconnect (HDI) layer between the ceramic substrate and the buffer layer, wherein the MLC is a tunable capacitor.

16. The thin film integrated circuit of claim 1 , wherein the ceramic substrate is Al 2 O 3 .

17. The thin film integrated circuit of claim 1 , wherein the ceramic substrate is AlN.

18. The thin film integrated circuit of claim 1 , wherein the ceramic substrate is Mg 2 SiO 4 .

19. The thin film integrated circuit of claim 1 , wherein the ceramic substrate is MgTiO 3 .

20. A thin film integrated circuit, comprising: a ceramic substrate; a glass dielectric buffer layer that overlies the ceramic substrate and has a surface polished to an Ra roughness less than or equal to 0.08 microns and substantially free of surface micropores, and is configured to withstand multiple anneals at high temperature in an oxidizing atmosphere without substantially affecting its surface quality; a thin film multi-level capacitor that is fabricated on the buffer layer surface and that includes at least one high permittivity dielectric layer between at least two electrode layers, the electrode layers being formed from a conductive thin film material; and an adhesion layer between the buffer layer and the MLC, wherein the adhesion layer includes one or more layers of thin film Al 2 O 3 .

21. The thin film integrated circuit of claim 1 , further comprising an adhesion layer between the buffer layer and the MLC, wherein the adhesion layer includes one or more layers of thin film TiO x .

22. The thin film integrated circuit of claim 20 , further comprising a high density interconnect (HDI) layer between the ceramic substrate and the buffer layer.