The present invention relates to a nonvolatile memory such as, for example a ROM or an EPROM, in which the information density of the memory is increased relative to a conventional nonvolatile memory that includes two logic state devices. Specifically, the nonvolatile memory of the present invention includes a SiN/TaN/SiN thin film resistor embedded within a material having a thermal conductivity of about 1 W/m-K or less; and a non-linear Si-containing device coupled to the resistor. Read and write circuits and operations are also provided in the present application.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A nonvolatile integrated circuit memory cell comprising a SiN/TaN/SiN thin film resistor embedded within a dielectric material having a thermal conductivity of about 1.00 W/m-K or less, said SiN/TaN/SiN thin film resistor is vertically oriented relative to a surface of an underlying semiconductor substrate; and a non-linear Si-containing device coupled to the resistor.
2. A nonvolatile integrated circuit memory chip comprising a write circuit in connection with a SiN/TaN/SiN thin film resistor cell, wherein said thin film resistor cell comprises first and second switching field effect transistors, wherein a terminal of the first switching field effect transistor and a terminal of the second switching field effect transistor are in parallel connection to a SiN/TaN/SiN thin film resistor, another terminal of the first switching field effect transistor is coupled to a first terminal of said resistor and another terminal of the second switching field effect transistor is coupled to a second terminal of said resistor; a read circuit, said read circuit comprising first and second voltage comparators in which the positive inputs are connected in parallel to one terminal end of a third switching field effect transistor; a current source coupled to one terminal end of a fourth switching field effect transistor, wherein the other terminal end of said fourth switching field effect transistor is coupled to said second terminal end of the memory cell, wherein said third and fourth switching field effect transistors including gates that are connected to each other in parallel and coupled to a digital signal of the read operation said first voltage comparator having its negative input coupled to a first reference voltage and said second voltage comparator having its negative input coupled a second reference voltage; and a decoder having two inputs coupled to outputs of the first and second voltage comparators.
3. The nonvolatile integrated circuit memory of claim 2 wherein said write circuit comprises: fifth and sixth switching field effect transistors having terminal ends in parallel arrangement coupled to a positive input terminal of a third voltage comparator, the negative input of the third voltage comparator is coupled to one terminal end of a seventh switching field effect transistor; output of said the third voltage comparator is coupled to one input of a two input NAND circuit, another terminal end of the fifth switching field transistor is coupled to a first threshold voltage, and a gate of the fifth switching field transistor is coupled to a digital signal for write “one” operation, another terminal end of said sixth switching field effect transistor is coupled to a second threshold voltage and a gate of the sixth switching field effect transistor is coupled to a digital signal for write “two” operation, another terminal end of the seventh switching field effect transistor is coupled to a terminal of the memory cell described above and a gate of the seventh switching field effect transistor and a gate of an eighth switching field effect transistor are connected in parallel and coupled to the digital signal of write operation, wherein another terminal end of the eighth switching field effect transistor and one terminal of a ninth discharge switching field effect transistor are connected in parallel and coupled to a terminal b of the voltage control current source unit, said ninth discharge field effect transistor having terminal ends that are coupled to terminal ends of a capacitor, another input of said two input NAND is coupled to a digital signal of write “zero”; the output of said NAND is coupled to the terminal c of the voltage control current source unit.
4. The nonvolatile integrated circuit memory chip of claim 2 wherein said SiN/TaN/SiN thin film resistor cell includes a SiN/TaN/SiN thin film resistor embedded within a dielectric material having a thermal conductivity of about 1 W/m-K or less.
5. The nonvolatile integrated circuit memory chip of claim 4 wherein said dielectric material is an interconnect dielectric layer.
6. The nonvolatile integrated circuit memory chip of claim 5 wherein said dielectric material comprises at least one of hydrogen silsesquioxane, methyl silsesquioxane, sol-gel porous silica, a carbon doped oxide, tetramethylsilane, trimethylsilane, methylsilane, a mixture of tetramethylsilane and a silane, or a SiO 2 .
7. The nonvolatile integrated circuit memory chip of claim 2 wherein said TaN undergoes a phase change as a function of an applied voltage.
8. The nonvolatile integrated circuit memory chip of claim 2 wherein said SiN/TaN/SiN thin film resistor is vertical or parallel to a surface of a semiconductor substrate.
9. The nonvolatile integrated circuit memory chip of claim 2 wherein said SiN/TaN/SiN thin film resistor cell provides a triple state or multi-state read only memory.
10. A nonvolatile integrated circuit memory chip comprising a write circuit in connection with a SiN/TaN/SiN thin film resistor cell, wherein said SiN/TaN/SiN thin film resistor cell includes a SiN/TaN/SiN thin film resistor embedded within a dielectric material having a thermal conductivity of about 1 W/m-K or less.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 24, 2008
February 1, 2011
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