The present invention relates to a semiconductor device including a semiconductor chip encapsulated by an encapsulation resin and a manufacturing method thereof, and an object of the invention is to provide the semiconductor chip and its manufacturing method in which the reduction in size may be attempted. It includes a semiconductor chip 15, an external connection terminal pad 18 electrically connected to the semiconductor chip 15, and an encapsulation resin 16 encapsulating the semiconductor chip 15, wherein a wiring pattern 12 on which the external connection terminal pad 18 is formed is provided between the semiconductor chip 15 and the external connection terminal pad 18, and the semiconductor chip 15 is flip-chip bonded to the wiring pattern 12.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: a semiconductor chip having an electrode pad, an external connection terminal pad electrically connected to the semiconductor chip, a wiring pattern, an insulating resin covering a first surface of the semiconductor chip, an upper surface of the wiring pattern, and a side surface of the wiring pattern, an encapsulation resin for encapsulating the semiconductor chip, and an upper surface and a side surface of the insulating resin, and a solder resist which is provided on a lower surface of the wiring pattern, a lower surface of the insulating resin, and a lower surface of the encapsulating resin and which is provided with an opening for exposing the external connection terminal pad, wherein the wiring pattern comprises: a chip connection region which is provided on an upper surface of the wiring pattern opposite to a first surface of the semiconductor chip on which the electrode pad is formed and to which the semiconductor chip is flip-chip bonded, and a pad formation region which is provided on a lower surface of the wiring pattern and on which the external connection terminal pad is formed.
2. The semiconductor device of claim 1 , wherein external connection terminal pad includes a Ni film and an Au film.
3. The semiconductor device of claim 1 , wherein an external connection terminal is provided on a bottom surface of the external connection terminal pad.
4. The semiconductor device of claim 1 , wherein a thickness of the encapsulation resin formed over the semiconductor chip is between about 30 um and about 60 um.
5. The semiconductor device of claim 1 , wherein a thickness of the insulating resin between the lower surface of the wiring pattern and the first surface of the semiconductor chip is about 20 um.
6. The semiconductor device of claim 1 , further including an internal connection terminal provided in the insulating resin, the internal connection terminal being connected to the electrode pad at one end and to the wiring pattern at the other end.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 17, 2007
February 8, 2011
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