NAND flash memory device with increased spacing between selection transistors and adjacent memory cells

1. A NAND flash memory device comprising: a drain selection transistor of a cell string provided on a semiconductor substrate; a source selection transistor of the cell string provided on the semiconductor substrate; a first memory cell of the cell string disposed adjacent to the drain selection transistor; a second memory cell of the cell string disposed adjacent to the source selection transistor; and third memory cells of the cell string located between the first and the second memory cells, wherein a first distance from the source selection transistor to the second memory cell is determined by adding a predetermined value to a second distance from a first of the third memory cells to a second of the third memory cells, wherein the first and second of the third memory cells are adjacently disposed and the predetermined value is a non-zero positive value, and a third distance from the drain selection transistor to the first memory cell is determined by subtracting the predetermined value from the second distance to prevent a chip size from increasing due to the first distance being greater than the second distance.

2. A NAND flash memory device comprising: a drain selection transistor of a cell string provided on a semiconductor substrate; a source selection transistor of the cell string provided on the semiconductor substrate; a first memory cell of the cell string disposed adjacent to the drain selection transistor; a second memory cell of the cell string disposed adjacent to the source selection transistor; third memory cells of the cell string located between the first and the second memory cells; and a trench formed in the semiconductor substrate at an area between a word line of the first memory cell and a drain selection line of the drain selection transistor, wherein the trench has a first surface distance that is greater than a second surface distance of the semiconductor substrate between each pair of adjacent third memory cells.

3. A NAND flash memory device comprising: a drain selection transistor of a cell string provided on a semiconductor substrate: a source selection transistor of the cell string provided on the semiconductor substrate; a first memory cell of the cell string disposed adjacent to the drain selection transistor; a second memory cell of the cell string disposed adjacent to the source selection transistor; third memory cells of the cell string located between the first and the second memory cells; and a trench formed in the semiconductor substrate at an area between a word line of the second memory cell and a source selection line of the source selection transistor, wherein the trench has a first surface distance that is greater than a second surface distance of the semiconductor substrate between each pair of adjacent third memory cells.

4. A NAND flash memory device comprising: a drain selection transistor of a cell string provided on a semiconductor substrate; a source selection transistor of the cell string provided on the semiconductor substrate; a first memory cell of the cell string disposed adjacent to the drain selection transistor; a second memory cell of the cell string disposed adjacent to the source selection transistor; third memory cells of the cell string located between the first and the second memory cells; a first trench formed in the semiconductor substrate at an area between a first word line of the first memory cell and a drain selection line of the drain selection transistor, wherein the first trench has a first surface distance that is greater than a second surface distance of the semiconductor substrate between each pair of adjacent third memory cells; and a second trench formed in the semiconductor substrate at an area between a second word line of the second memory cell and a source selection line of the source selection transistor, wherein the second trench has a third surface distance that is greater than the second surface distance of the semiconductor substrate between each pair of adjacent third memory cells.