Thin, smooth silicon-containing films are prepared by deposition methods that utilize a silicon containing precursor. In preferred embodiments, the methods result in Si-containing films that are continuous and have a thickness of about 150 Å or less, a surface roughness of about 5 Å rms or less, and a thickness non-uniformity of about 20% or less. Preferred silicon-containing films display a high degree of compositional uniformity when doped or alloyed with other elements. Preferred deposition methods provide improved manufacturing efficiency and can be used to make various useful structures such as wetting layers, HSG silicon, quantum dots, dielectric layers, anti-reflective coatings (ARC's), gate electrodes and diffusion sources.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An integrated circuit comprising a continuous amorphous Si-containing film having a thickness that is 15 Å or greater and that is 150 Å or less, a surface area of about one square micron or greater, and a thickness non-uniformity of about 10% or less for a mean film thickness in the range of 100 Å to 150 Å, a thickness non-uniformity of about 15% or less for a mean film thickness in the range of 50 Å to 99 Å, and a thickness non-uniformity of about 20% or less for a mean film thickness of less than 50 Å.
2. The integrated circuit of claim 1 , further comprising a dielectric material having a surface in contact with the Si-containing film, wherein the surface in contact has an area of about 0.5 square micron or greater.
3. The integrated circuit of claim 2 , wherein the dielectric material is selected from the group consisting of silicon oxide, metal oxide, metal silicate, silicon oxynitride and silicon nitride.
4. The integrated circuit of claim 1 , wherein the Si-containing film further comprises a dopant element selected from the group consisting of boron, arsenic, and phosphorous.
5. The integrated circuit of claim 4 , wherein the dopant element is uniformly distributed throughout the Si-containing film.
6. The integrated circuit of claim 1 , wherein the Si-containing layer further comprises germanium.
7. The integrated circuit of claim 1 , wherein the Si-containing layer further comprises carbon.
8. The integrated circuit of claim 1 , wherein the Si-containing film has a surface roughness of about 5 Å rms or less.
9. The integrated circuit of claim 1 , wherein the Si-containing film has a surface roughness of about 3 Å rms or less.
10. The integrated circuit of claim 1 , wherein the Si-containing film has a surface roughness of about 2 Å rms or less.
11. The integrated circuit of claim 1 , further comprising a non-single crystal material having a surface in contact with the Si-containing film.
12. The integrated circuit of claim 1 , further comprising a doped Si-containing layer having a surface in contact with the Si-containing film.
13. The integrated circuit of claim 1 , further comprising a trench in contact with the Si-containing film.
14. The integrated circuit of claim 1 , wherein the Si-containing film is a diffusion layer.
15. The integrated circuit of claim 1 , wherein the Si-containing film is a Si—N film.
16. The integrated circuit of claim 15 , wherein the Si—N film has a hydrogen content that is less than about 4 atomic %.
17. A transistor gate electrode comprising a semiconductor substrate, a dielectric layer over the semiconductor substrate, a continuous amorphous Si-containing film having a thickness of about 125 Å or less and a thickness non-uniformity of about 20% or less, and a doped semiconductor layer over the continuous amorphous Si-containing film.
18. The transistor gate electrode of claim 17 , wherein the doped semiconductor layer is selected from the group consisting of Si—Ge, Si—C, and Si—Ge—C.
19. The transistor gate electrode of claim 17 , wherein the amorphous Si-containing film has a surface roughness of about 5 Å rms or less.
20. The transistor gate electrode of claim 17 , wherein the Si-containing film has a thickness of about 100 Å or less.
21. The transistor gate electrode of claim 17 , wherein the Si-containing film has a thickness of about 80 Å or less.
22. The transistor gate electrode of claim 17 , further comprising a dielectric material having a surface in contact with the Si-containing film, wherein the surface in contact has an area of about 5 square microns or greater.
23. The transistor gate electrode of claim 17 , further comprising a dielectric material having a surface in contact with the Si-containing film, wherein the surface in contact has an area of about 10 square microns or greater.
24. The transistor gate electrode of claim 17 , wherein the Si-containing film is a conformal coating.
25. The transistor gate electrode of claim 17 , further comprising a non-single crystal layer having a surface in contact with the Si-containing film, wherein the non-single crystal layer is selected from the group consisting of silicon oxide, metal oxide, metal silicate, silicon oxynitride and silicon nitride.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 12, 2007
February 22, 2011
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