Patentable/Patents/US-7894272
US-7894272

Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition

PublishedFebruary 22, 2011
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A computer program product for operating a memory cell and memory array. The computer program product of memory cell operation entails receiving a request to read a binary value stored in the memory cell. A pre-charging operation pre-charges a bit-line capacitor in an electronic circuit formed by the memory cell to a pre-charge voltage. A word-line in the electronic circuit is then activated. A discharging operation discharges the bit-line capacitor through the said memory cell in the electronic circuit to the word-line. Additionally, an electron discharge time measurement is started when the word-line is activated. The electron discharge time measurement is stopped when the voltage level in the bit-line falls below a pre-defined reference voltage. A determining operation determines the binary value from the measured electron discharge time.

Patent Claims
6 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A computer program product comprising a computer useable medium including a computer readable program for operating a memory cell in which a variation of the characteristic parameter of the memory cell affects the effective resistance of the memory cell, the computer readable program comprising computer code to: receive a request to read a binary value stored in the memory cell; pre-charge a bit-line capacitor in an electronic circuit formed, at least partially, by the memory cell to a pre-charge voltage; activate a word-line in the electronic circuit; discharge the bit-line capacitor through the said memory cell in the electronic circuit to the word-line; start an electron discharge time measurement when the word-line is activated; stop the electron discharge time measurement when the voltage level in the bit-line falls below a pre-defined reference voltage; and determine the binary value from the measured electron discharge time; wherein the pre-defined reference voltage is a fraction of the pre-charge voltage.

2

2. The computer program product of claim 1 , wherein the computer code to determine the binary value from the electron discharge time includes: compare the measured electron discharge time with different target discharge times associated with the binary values; and determine the binary value stored in the memory cell with the associated target discharge time closest to the electron discharge time.

3

3. The computer program product of claim 2 , further comprising computer code to assign a different target discharge time for each of the possible binary values represented in the memory cell.

4

4. The computer program product of claim 1 , wherein the characteristic parameter in the memory cell is a resistance level.

5

5. The computer program product of claim 1 , wherein the characteristic parameter in the memory cell is an electron charge level.

6

6. The computer program product of claim 1 , wherein the electronic circuit includes an intrinsic resistor-capacitor circuit.

Classification Codes (CPC)

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Patent Metadata

Filing Date

February 2, 2010

Publication Date

February 22, 2011

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Cite as: Patentable. “Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition” (US-7894272). https://patentable.app/patents/US-7894272

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