Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to a method for forming a microsystem and one or more passive devices in the microsystem. Layers of epoxy are sequentially deposited over a substrate to form multiple planarized layers of epoxy over the substrate. The epoxy layers are deposited by spin coating. At least some of the epoxy layers are photolithographically patterned after they are deposited and before the next epoxy layer is deposited. An integrated circuit having multiple I/O bond pads is placed on an associated epoxy layer. At least one conductive interconnect layer is formed over an associated epoxy layer. A passive component is formed within at least one of the epoxy layers. The passive component is electrically coupled with the integrated circuit via at least one of the interconnect layers. Multiple external package contacts are formed. The integrated circuit is electrically connected to the external package contacts at least partly through one or more of the conductive interconnect layers. Various embodiments pertain to apparatuses that are formed by performing some or all of the aforementioned operations.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A wafer level method for packaging integrated circuits, the method comprising: sequentially depositing layers of epoxy over a substrate to form a multiplicity of planarized layers of epoxy over the substrate, the epoxy layers including a first epoxy layer and a second epoxy layer, wherein the epoxy layers are deposited by spin coating, there being a topmost epoxy layer; photolithographically patterning at least one of the epoxy layers after the at least one of the epoxy layers is deposited and before the next epoxy layer is deposited; forming openings in the at least one of the epoxy layers after the at least one of the epoxy layers is patterned and before the next epoxy layer is deposited; placing an integrated circuit within an associated one of the openings, wherein the integrated circuit has a plurality of I/O bond pads and at least one of the epoxy layers is deposited after the placement of the integrated circuit to thereby cover the integrated circuit; forming at least one conductive interconnect layer, wherein each interconnect layer is formed over an associated epoxy layer; forming a first passive component within at least one of the multiplicity of epoxy layers, wherein the first passive component is electrically coupled with the integrated circuit via at least one of the interconnect layers, wherein the formation of the first passive component comprises: sputtering a ferromagnetic material on one of the sequentially deposited epoxy layers to form a magnetic core; depositing one of the sequentially deposited epoxy layers on the magnetic core; and sputtering a conductive material on the epoxy layer deposited over the magnetic core to form an inductor winding configured to be magnetically coupled with the magnetic core, wherein the first passive component is an inductor that includes the magnetic core and the inductor winding and wherein the first passive component is embedded at least in the first epoxy layer; forming a second passive component, wherein the second passive component does not directly overlie the first passive component and is positioned within an epoxy layer selected from a group consisting of the first epoxy layer and the second epoxy layer, the second epoxy layer being distinct from the first epoxy layer, wherein the second passive component is electrically coupled to at least one of the interconnect layers; and forming a multiplicity of external package contacts, wherein the integrated circuit is electrically connected to a plurality of the external package contacts at least in part through at least one of the conductive interconnect layers.
2. The method of claim 1 wherein at least a part of the formation of the first passive component is performed substantially concurrently with at least a part of the formation of one of the interconnect layers.
3. The method of claim 1 wherein the second passive component is one of a group consisting of: a resistor, a capacitor, an inductor, a magnetic core, a MEMs device, a sensor and a photovoltaic cell.
4. The method of claim 1 wherein the second passive component is a thin film resistor and the formation of the second passive component is performed by sputtering a conductive metal over at least one of the epoxy layers to form the thin film resistor.
5. The method of claim 1 wherein the second passive component is a capacitor and the formation of the second passive component includes forming metal layers and a dielectric layer such that the dielectric layer is sandwiched between the first and second metal layers.
6. The method of claim 1 wherein the second passive component is a magnetic core and the formation of the second passive component includes sputtering a ferromagnetic material on at least one of the epoxy layers to form the magnetic core.
7. The method of claim 1 wherein: the substrate has a first surface and an opposing second surface; the stacked epoxy layers are deposited over the first surface of the substrate; and the method comprising: etching the second surface of the substrate to form a cavity; electroplating a conductive metal into the cavity to form a capacitor; and forming conductive vias within the substrate such that at least some of the vias are electrically coupled with the capacitor.
8. The method of claim 1 wherein: at least one of the interconnect layers is positioned between the first and second passive components.
9. The method of claim 1 comprising forming a plurality of micro-modules, wherein: each micro-module is formed by the sequential depositing of the layers of epoxy, the photolithographic patterning of the at least one of the epoxy layers, the forming of openings in the at least one of the epoxy layers, the placing of the integrated circuit, the forming of the at least one interconnect layer, the forming of the first passive component, the forming of the second passive component and the forming of the multiplicity of external package contacts; and at least a portion of each micro-module is formed concurrently with at least a portion of the other micro-modules.
10. The method as recited in claim 1 , wherein: there is a vertical axis and a horizontal axis, the horizontal axis being perpendicular to the vertical axis; the sequential depositing of the epoxy layers is performed along the vertical axis and not along the horizontal axis; and the second passive component does not overlie the first passive component when the second passive component is offset from the first passive component along the horizontal axis.
11. A wafer level method for packaging integrated circuits, the method comprising: sequentially depositing layers of planarizing, photo-imageable epoxy over a substrate to form a multiplicity of planarized layers of epoxy over the substrate, the planarizing, photo-imageable epoxy layers including a first epoxy layer, a second epoxy layer and a third epoxy layer, wherein the epoxy layers are deposited by spin coating; photolithographically patterning at least one of the epoxy layers after the at least one of the epoxy layers is deposited and before the next epoxy layer is deposited, wherein the photolithographic patterning causes exposed portions of each patterned epoxy layer to at least partially crosslink; forming openings in the at least one of the epoxy layers after the at least one of the epoxy layers is patterned by removing unexposed portions of the patterned epoxy; forming a plurality of conductive interconnect layers, wherein each interconnect layer is formed on an associated epoxy layer and is formed at least in part by electroplating; placing an integrated circuit within an associated one of the openings, wherein the integrated circuit has a plurality of I/O bond pads and at least one of the epoxy layers is deposited after the placement of the integrated circuit to thereby cover the integrated circuit; forming a plurality of conductive vias, wherein each conductive via is associated with an associated interconnect layer and an associated epoxy layer and is formed within an associated one of the openings in the associated epoxy layer and is formed at least in part during the electroplating of the associated interconnect layer; sputtering a conductive material over at least one of the epoxy layers to form at least one thin film resistor; sputtering a ferromagnetic material over at least one of the epoxy layers to form at least one magnetic core; electroplating a conductive material over at least one of the epoxy layers to form at least one inductor winding, wherein each of the at least one thin film resistor, at least one magnetic core and at least one inductor winding is formed between and encapsulated by sequentially deposited layers of epoxy and is electrically coupled with at least one of the interconnect layers; and forming a multiplicity of external package contacts, wherein the integrated circuit is electrically connected to a plurality of the external package contacts at least in part through at least one of the conductive interconnect layers and at least one of the conductive vias.
12. A wafer level method for packaging integrated circuits, the method comprising: sequentially depositing layers of epoxy over a substrate to form a multiplicity of planarized layers of epoxy over the substrate, the epoxy layers including a first epoxy layer and a second epoxy layer, wherein the epoxy layers are deposited by spin coating, there being a topmost epoxy layer; photolithographically patterning at least one of the epoxy layers after the at least one of the epoxy layers is deposited and before the next epoxy layer is deposited; forming openings in the at least one of the epoxy layers after the at least one of the epoxy layers is patterned and before the next epoxy layer is deposited; placing an integrated circuit within an associated one of the openings, wherein the integrated circuit has a plurality of I/O bond pads and at least one of the epoxy layers is deposited after the placement of the integrated circuit to thereby cover the integrated circuit; forming at least one conductive interconnect layer, wherein each interconnect layer is formed over an associated epoxy layer; forming a first passive component within at least one of the multiplicity of epoxy layers, wherein the first passive component is electrically coupled with the integrated circuit via at least one of the interconnect layers, wherein the formation of the first passive component comprises: depositing a first metal layer on one of the epoxy layers; forming a dielectric layer on the first metal layer; and depositing a second metal layer such that the dielectric layer is sandwiched between the first and second metal layers, wherein the first passive component is a capacitor that includes the first and second metal layers and the dielectric layer and wherein the first passive component is embedded at least in the first epoxy layer; forming a second passive component, wherein the second passive component does not directly overlie the first passive component and is positioned within an epoxy layer selected from a group consisting of the first epoxy layer and the second epoxy layer, the second epoxy layer being distinct from the first epoxy layer, wherein the second passive component is electrically coupled to at least one of the interconnect layers; and forming a multiplicity of external package contacts, wherein the integrated circuit is electrically connected to a plurality of the external package contacts at least in part through at least one of the conductive interconnect layers.
13. The method as recited in claim 12 , wherein: there is a vertical axis and a horizontal axis, the horizontal axis being perpendicular to the vertical axis; the sequential depositing of the epoxy layers is performed along the vertical axis and not along the horizontal axis; and the second passive component does not overlie the first passive component when the second passive component is offset from the first passive component along the horizontal axis.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 5, 2009
March 8, 2011
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