Semiconductor memory device

1. A semiconductor memory device, comprising: an internal power generator for negative-pumping an external power to generate a bulk voltage to be applied to a bulk end of cell; a refresh unit for generating an internal refresh signal for a refresh driving at regular intervals during a self refresh mode; a level controller for controlling a level of the bulk voltage in the self refresh mode; and a period adjustor for adjusting the regular intervals when the level controller is driven.

2. The semiconductor memory device as recited in claim 1 , wherein the internal power generator includes: a charge pumping circuit for negative-pumping the external power to produce the bulk voltage; a level sensor for sensing a level of the bulk voltage corresponding to a level of an adjusted reference voltage under the control of the level controller; an oscillator for generating a period signal in response to a sending signal of the level sensor; and a pumping control signal generator for controlling the operation of the charge pumping circuit in response to the period signal.

3. The semiconductor memory device as recited in claim 2 , wherein the level sensor includes: a feedback circuit for providing a level of the bulk voltage on the basis of the reference voltage as a feedback voltage, the level of the feedback voltage being adjusted under the control of the level controller; and a differential amplifier for taking the feedback voltage and its inverted feedback voltage to output the sensing signal.

4. The semiconductor memory device as recited in claim 3 , wherein the level controller includes: a first NAND gate taking a self refresh interval signal notifying that the current operation is in the self refresh mode and a first level adjustment signal; a first inverter for inverting an output signal of the first NAND gate to provide a down-control signal; a second NAND gate taking the self refresh interval signal and a second level adjustment signal; and a second inverter for inverting an output signal of the second NAND gate to output an up-control signal.

5. The semiconductor memory device as recited in claim 4 , wherein the first and the second level adjustment signals are selected so that a leakage current is minimized in a test step of wafer level, and set by a fuse option or a metal option.

6. The semiconductor memory device as recited in claim 5 , wherein the feedback circuit includes: first to fourth PMOS transistors whose each gate takes a ground voltage and which are connected in series between the reference voltage and an output node; fifth to eighth PMOS transistors whose each gate takes the internal voltage and which are connected in series between the output node and the ground voltage; a first NMOS transistor whose gate receives the down-control signal and which is connected in parallel with the first PMOS transistor; and a second NMOS transistor whose gate accepts the up-control signal and which is connected in parallel with the eighth PMOS transistor.

7. The semiconductor memory device as recited in claim 2 , wherein the refresh unit includes: a refresh exit/entry controller for taking a clock enable signal and an auto refresh command and generating a self refresh interval signal notifying that the current operation is in a self refresh mode; and a control signal generator for periodically generating an internal refresh signal and an internal address for refresh driving during activation of the self refresh interval signal, an activation period of the internal refresh signal-varying in response to a period adjustment signal of the interval controller.

8. The semiconductor memory device as recited in claim 7 , wherein the control signal generator includes: a refresh period signal generator for periodically outputting a period-pulse signal during activation of the self refresh interval signal, the period of the period-pulse signal being adjusted in response to the period adjustment signal; an internal refresh signal generator for periodically outputting a period-pulse signal during activation of the self refresh interval signal, the internal refresh signal being activated in response to the period-pulse signal; an internal address counter for increasing a row address by one bit unit in response to the internal refresh signal, to output the internal address.

9. The semiconductor memory device as recited in claim 8 , wherein the period adjustor includes a NOR gate for taking the first and the second level adjustment signals to output the period adjustment signal.

10. The semiconductor memory device as recited in claim 9 , wherein the refresh period signal generator includes: an oscillator for generating the period signal during activation of the self refresh interval signal, the period of the period signal being extended upon activation of the period adjustment signal; and a pulse generator for generating the period-pulse signal of pulse type whenever the period signal is activated.

11. The semiconductor memory device as recited in claim 10 , wherein the oscillator includes: a driving voltage supplier for adjusting a level of a driving voltage in response to the period adjustment signal to supply an adjusted driving voltage; and an inverter chain for generating the period signal having a period corresponding to the level of the driving voltage during activation of the self refresh interval signal.

12. The semiconductor memory device as recited in claim 11 , wherein the driving voltage supplier includes: a plurality of resistors coupled in series between an external voltage and a ground voltage; an NMOS transistor whose gate takes the period adjustment signal and which is connected in parallel with one of the plurality of resistors, voltages divided by the plurality of resistors being outputted as a first and a second driving voltages.