A semiconductor device has a semiconductor chip provided with an insulating layer formed so as to be thinner in a first secondary-wire-free area than in a first secondary-wire-containing area. Further, the semiconductor chip has an edge extending further outward than a side wall, which severs as an edge of an upper insulating layer, in an extending direction of a circuit-forming surface of the semiconductor chip on which electrode pads are provided. This makes it possible to provide a semiconductor device capable of suppressing electromagnetic interference between a secondary wire and an electronic circuit of a semiconductor chip and the curvature of a wafer even in the case of overlap between the secondary wire and the electronic circuit, and of reducing the risk of occurrence of chipping in a dicing step.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: a semiconductor chip having a circuit-forming surface provided with an electrode pad; a lower insulating layer, covering the semiconductor chip, which is provided with an opening via which the electrode pad is partially exposed; a secondary wire including (i) a pad section for making an electrical connection to the electrode pad by making contact with an exposed portion of the electrode pad, (ii) a land section including an external connection terminal for making an electrical connection between the electrode pad and an external circuit provided outside of the semiconductor device, and (iii) a wiring section for making an electrical connection between the pad section and the land section; and an upper insulating layer, covering the secondary wire, which is provided with an opening via which at least the external connection terminal of the land section of the secondary wire is exposed, at least the wiring section of the secondary wire being provided on the lower insulating layer, a total thickness of insulating layers, provided in a secondary-wire-free area excluding a secondary-wire-containing area where at least the wiring section of the secondary wire is provided, which include at least the lower insulating layer being less than a total thickness of the lower insulating layer and the upper insulating layer in the secondary-wire-containing area, excluding the land section, the semiconductor chip having an edge extending further outward than an edge of the upper insulating layer in an extending direction of a surface of the semiconductor chip on which the electrode pad is provided, wherein: the lower insulating layer comprises a first lower insulating layer and a second lower insulating layer, wherein the first lower insulating layer is made of an oxide film or a nitride film, and the second lower insulating layer is made of an organic film, the semiconductor chip further includes an electronic circuit for processing an analog signal which electronic circuit is provided on the circuit-forming surface; and the lower insulating layer has a predetermined value of thickness for each specific area of the semiconductor chip such that a degree of electromagnetic interference between the secondary wire and the electronic circuit is suppressed.
2. The semiconductor device as set forth in claim 1 , wherein the secondary-wire-free area excludes the secondary-wire-containing area and an area around the secondary-wire-containing area.
3. The semiconductor device as set forth in claim 1 , wherein the lower insulating layer is thinner in the secondary-wire-free area than in the secondary-wire-containing area.
4. The semiconductor device as set forth in claim 2 , wherein: the upper insulating layer is provided in the secondary-wire-free area; and a total thickness of the lower insulating layer and the upper insulating layer in the secondary-wire-free area is not greater than a thickness of the lower insulating layer in the secondary-wire-containing area.
5. The semiconductor device as set forth in claim 2 , wherein the upper insulating layer is not provided in the secondary-wire-free area.
6. The semiconductor device as set forth in claim 1 , wherein: the electrode pad is provided underneath the land section of the secondary wire; and the secondary-wire-free area further excludes an area provided with the land section underneath which the electrode pad is provided.
7. A semiconductor device comprising: a semiconductor chip having a circuit-forming surface provided with an electrode pad; a lower insulating layer, covering the semiconductor chip, which is provided with an opening via which the electrode pad is partially exposed; a secondary wire having a part electrically connected to the electrode pad by making contact with an exposed portion of the electrode pad and further including a wiring section provided so as to be run onto the lower insulating layer; and an upper insulating layer covering at least the wiring section of the secondary wire, a total thickness of insulating layers, provided in a secondary-wire-free area excluding a secondary-wire-containing area where at least the wiring section of the secondary wire is provided, which include at least the lower insulating layer being less than a total thickness of the lower insulating layer and the upper insulating layer in the secondary-wire-containing area, excluding a land section including an external connection terminal for making an electrical connection between the electrode pad and an external circuit provided outside of the semiconductor device, the semiconductor chip having an edge extending further outward than an edge of the upper insulating layer in an extending direction of a surface of the semiconductor chip on which the electrode pad is provided, wherein the lower insulating layer comprises a first lower insulating layer and a second lower insulating layer, wherein the first lower insulating layer is made of an oxide film or a nitride film, and the second lower insulating layer is made of an organic film; the semiconductor chip further includes an electronic circuit for processing an analog signal which electronic circuit is provided on the circuit-forming surface; and the lower insulating layer has a predetermined value of thickness for each specific area of the semiconductor chip such that a degree of electromagnetic interference between the secondary wire and the electronic circuit is suppressed.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 25, 2008
March 15, 2011
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