A semiconductor memory device for storing data defining a multidimensional space based on coordinate information of the data, includes: a cell array having memory cells arranged in a lattice pattern, for storing the data; a word line selector selecting and driving any one of a plurality of word lines which activate memory cells arranged in a row direction; write amplifiers/sense amplifiers writing/reading data to/from the memory cells arranged in a column direction; an amplifier selector inputting/outputting the data to/from the selected one of the write amplifiers/sense amplifiers; and an address conversion circuit generating a row address to be supplied to the word line selector based on the coordinate information of the data, and to generate a column address to be supplied to the amplifier selector by converting the coordinate information of the data into one-dimensional information.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor memory device to store data defining a multidimensional space, based on coordinate information of the data, the semiconductor device comprising: a cell array including memory cells arranged in a lattice pattern to store the data; a word line selector selecting and driving any one of a plurality of word lines to activate the memory cells arranged in a row direction; a plurality of write amplifiers and a plurality of sense amplifiers writing and reading the data to and from the memory cells, respectively, arranged in a column direction; an amplifier selector selecting any one of a plurality of pairs of the write amplifiers and the sense amplifiers to input and output the data to and from the selected one of the plurality of pairs of the write amplifiers and the sense amplifiers, respectively; and an address conversion circuit generating a row address to be supplied to the word line selector based on the coordinate information of the data, and to generate a column address to be supplied to the amplifier selector by converting the coordinate information of the data into one-dimensional information.
2. The semiconductor memory device according to claim 1 , wherein the address conversion circuit generates the row address by using bit values of a plurality of pieces of data having common values as address values indicating the coordinate information.
3. The semiconductor memory device according to claim 1 , wherein the address conversion circuit generates the column address by using a combination of bit values of a plurality of pieces of data having different values as address values indicating the coordinate information.
4. The semiconductor memory device according to claim 1 , wherein the address conversion circuit assigns a terminal address to an input/output terminal number associated with the data to generate the column address with a combination of the terminal address and the coordinate information.
5. The semiconductor memory device according to claim 1 , wherein the address conversion circuit assigns a data address to each bit of a plurality of bits when a value of the data is set by using the plurality of bits, to generate the column address by using a combination of the data address and the coordinate information.
6. The semiconductor memory device according to claim 1 , wherein the address conversion circuit divides a size of the space into small spaces each having a size defined by using the number of data represented by a power of 2, and assigns a small space address to a number indicating each of the small spaces, to generate the column address by using a combination of the small space address and the coordinate information.
7. The semiconductor memory device according to claim 1 , wherein the address conversion circuit includes a plurality of image mapping circuits corresponding to each size of the space of the data, and selects one of the image mapping circuits in response to an image size selection signal for specifying the size of the space of the data.
8. The semiconductor memory device according to claim 7 , wherein the plurality of image mapping circuits each perform address conversion according to a rule predefined for each size of the space of the data.
9. The semiconductor memory device according to claim 1 , wherein the semiconductor memory device performs a burst operation to sequentially input and output a plurality of pieces of data.
10. The semiconductor memory device according to claim 1 , wherein the semiconductor memory device performs a full page operation to access the plurality of memory cells connected to a single word line through one address input.
11. The semiconductor memory device according to claim 1 , further comprising a reset control circuit to control all the memory cells to be brought into a reset state before writing the data to the plurality of memory cells.
12. The semiconductor memory device according to claim 1 , wherein the semiconductor memory device is formed on a semiconductor substrate having the address conversion circuit different from other functional blocks.
13. The semiconductor memory device according to claim 12 , further comprising a latch circuit to temporarily store address data transmitted from a transmission-side device to a pre-stage of the address conversion circuit so as to transmit address data selected from among the address data to the address conversion circuit in response to a command signal transmitted from the transmission side device, for specifying an operation of the semiconductor memory device.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 9, 2008
March 15, 2011
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