Patentable/Patents/US-7915686
US-7915686

Semiconductor device and manufacturing of the same

PublishedMarch 29, 2011
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

An object of the present invention is to improve the performance of a semiconductor device having a CMISFET. Each of an n channel MISFET and a p channel MISFET which form the CMISFET includes a gate insulating film composed of a silicon oxynitride film and a gate electrode including a silicon film positioned on the gate insulating film. Metal elements such as Hf are introduced near the interface between the gate electrode and the gate insulating film with a surface density of 1×1013 to 5×1014 atoms/cm2. The impurity concentration of channel regions of the n channel MISFET and the p channel MISFET is controlled to be equal to or lower than 1.2×1018/cm3.

Patent Claims
6 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A semiconductor device comprising: a semiconductor substrate; a first MISFET of an n channel type formed on said semiconductor substrate; and a second MISFET of a p channel type formed on said semiconductor substrate; wherein a gate insulating film of each of said first and second MISFETs consists essentially of a silicon oxide film or a silicon oxynitride film, a gate electrode of each of said first and second MISFETs includes a conductive silicon film positioned on said gate insulating film, monatomic metal elements are introduced near an interface between said gate electrode and said gate insulating film in each of said first and second MISFETs such that metal atoms with a surface density of 1×10 13 to 5×10 14 atoms/cm 2 are contained in a region within 0.5 nm upward and downward from the interface and metal atoms are not contained in a region of the gate insulating film and the gate electrode separated by more than 0.5 nm from the interface, respectively, and a channel region of each of said first and second MISFETs contains an impurity the concentration of which is equal to or lower than 1.2×10 18 /cm 3 .

2

2. The semiconductor device according to claim 1 , wherein said monatomic metal elements are capable of forming both a donor level and an acceptor level in a band gap of crystal silicon.

3

3. The semiconductor device according to claim 2 , wherein said monatomic metal elements are any one of Hf, Zr, Pt, Mo and W.

4

4. The semiconductor device according to claim 1 , wherein said monatomic metal elements include first metal atoms capable of forming an acceptor level in a band gap of crystal silicon and second metal atoms capable of forming a donor level in the band gap of the crystal silicon.

5

5. The semiconductor device according to claim 4 , wherein said first metal atoms are any one of Hf, Zr, Pt, Mo, W, Ni, and Al, and wherein said second metal atoms are any one of Hf, Zr, Pt, Mo, W, Ti, and Ta.

6

6. The semiconductor device according to claim 1 , wherein said monatomic metal elements introduced near the interface between the gate electrode and the gate insulating film in said first MISFET are metal atoms that are capable of forming an acceptor level in a band gap of crystal silicon, and wherein said monatomic metal elements introduced near the interface between the gate electrode and the gate insulating film in said second MISFET are metal atoms that are capable of forming a donor level in the band gap of the crystal silicon.

Classification Codes (CPC)

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Patent Metadata

Filing Date

May 24, 2006

Publication Date

March 29, 2011

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