Integrated circuit devices with multi-dimensional pad structures

1. An integrated circuit package, comprising: a first package substrate; an integrated circuit (IC) stack structure formed over the first package substrate, comprising a plurality of device layers, wherein one of the device layers comprises opposing top and bottom surfaces, a plurality of sidewall surfaces surrounding the top and bottom surfaces, and a first pad exposed by one of the sidewall surfaces thereof, and wherein an underlying device layer of the device layers comprises a second pad exposed by a sidewall surface thereof, an overlying device layer of the device layers comprises a third pad exposed by a sidewall surface thereof, and the third pad substantially overlies the second pad to form a composite pad, and wherein the second pad physically contacts the underlying device layer of the device layers and the third pad physically contacts the overlying device layer of the device layers; and a second packaging substrate electrically bonded to the composite pad from a sidewall of the IC stack structure.

2. The integrated circuit package as claimed in claim 1 , wherein the underlying device layer comprises a plurality of second pads exposed by at least one sidewall surface thereof, the overlying device layer comprises a plurality of third pads exposed by at least one sidewall surface thereof, and the third pads substantially overlie the second pads, respectively, to form a plurality of composite pads.

3. The integrated circuit package as claimed in claim 1 , further comprising a fourth pad formed in a topmost device layer of the device layers and the fourth pad is exposed by a top surface thereof.

4. The integrated circuit package as claimed in claim 1 , further comprising a fourth pad formed in a bottommost device layer of the device layers, wherein the IC package further comprises at least one second conductive bonding formed thereon, electrically connecting the fourth pad and the second conductive bonding.

5. An integrated circuit package, comprising: a first package substrate; an integrated circuit (IC) stack structure partially embedded in the first package substrate, comprising a plurality of device layers, wherein one of the device layers comprises opposing top and bottom surfaces, a plurality of sidewall surfaces surrounding the top and bottom surfaces, and a first pad exposed by one of the sidewall surfaces thereof, and wherein a underlying device layer of the device layers comprises a second pad exposed by a sidewall surface thereof, an overlying device layer of the device layers comprises a third pad exposed by a sidewall surface thereof, and the third pad substantially overlies the second pad to form a composite pad, and wherein the second pad physically contacts the underlying device layer of the device layers and the third pad physically contacts the overlying device layer of the device layers; and a second packaging substrate electrically bonded to the composite pad from a sidewall of the IC stack structure.

6. The integrated circuit package as claimed in claim 5 , wherein the underlying device layer comprises a plurality of second pads exposed by at least one sidewall surface thereof, the overlying device layer comprises a plurality of third pads exposed by at least one sidewall surface thereof, and the third pads substantially overlie the second pads, respectively, to form a plurality of composite pads.

7. The integrated circuit package as claimed in claim 5 , further comprising a fourth pad formed in a topmost device layer of the device layers and the fourth pad is exposed by a top surface thereof.

8. The integrated circuit package as claimed in claim 5 , further comprising a fourth pad formed in a bottommost device layer of the device layers, wherein the IC package further comprises at least one second conductive bonding formed thereon, electrically connecting the fourth pad and the second conductive bonding.

9. An integrated circuit package, comprising: a first package substrate; an integrated circuit (IC) stack structure embedded in the first package substrate, comprising a plurality of device layers, wherein one of the device layers comprises opposing top and bottom surfaces, a plurality of sidewall surfaces surrounding the top and bottom surfaces, and a first pad exposed by the top surface thereof, and wherein the top surface of the IC stack structure is coplanar with a surface of the first package substrate where the bond pad is formed; and a second packaging substrate electrically bonded to the first pad from a top surface of the IC stack structure.

10. The integrated circuit package as claimed in claim 9 , wherein a underlying device layer of the device layers comprises a second pad exposed by a sidewall surface thereof, an overlying device layer of the device layers comprises a third pad exposed by a sidewall surface thereof, the third pad substantially overlies the second pad to form a composite pad, a topmost device layer of the IC stack structure comprises a fourth pad exposed by an top surface thereof and the integrated circuit (IC) stack is substantially coplanar with the first package substrate.

11. The integrated circuit package as claimed in claim 10 , wherein the underlying device layer comprises a plurality of the second pads exposed by at least one sidewall surface thereof, the overlying device layer comprises a plurality of the third pads exposed by at least one sidewall surface thereof, wherein the third pads substantially overlie the second pads, respectively, to form a plurality of the composite pads.

12. The integrated circuit package as claimed in claim 11 , the first package substrate further comprising at least one internal wiring embedded therein, electrically connecting the composite pad.