A semiconductor memory device includes a memory cell array having at least one memory bank. The memory bank being divided into memory blocks such that the memory blocks have a block position including at least one edge memory block at an edge of the memory bank and at least one non-edge memory block. Each memory block includes a plurality of memory cells. Each memory cell associated with at least one bit line and at least one word line. The semiconductor memory device includes a refresh execution circuit configured to activate a less than or equal number of word lines one at a time during a refresh operation for the memory cells in the edge memory block as activated one at a time during a refresh operation for the memory cells in the non-edge memory block.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor memory device, comprising: a memory cell array having at least one memory bank, the memory bank being divided into memory blocks such that the memory blocks have a block position including at least one edge memory block at an edge of the memory bank and at least one non-edge memory block, each memory block including a plurality of memory cells, each memory cell associated with at least one bit line and at least one word line; and a refresh execution circuit configured to activate a less than or equal number of word lines one at a time during a refresh operation for the memory cells in the edge memory block as activated one at a time during a refresh operation for the memory cells in the non-edge memory block, wherein the at least one edge memory block is configured such that the refresh operation involves a plurality of word lines, and the refresh execution circuit is configured to perform the refresh operation on the memory cells in the edge memory block in a first and second stage, and configured to activate a first number of the plurality of word lines one at a time in the first stage and to activate a second number of the plurality of word lines one at a time in the second stage, such that each of the plurality of word lines is activated during the refresh operation.
2. The device of claim 1 , wherein the first number equals the second number.
3. The device of claim 2 , wherein the first number equals a number of word lines activated one at a time during the refresh operation for the memory cells in the non-edge memory block.
4. The device of claim 1 , wherein the first number is greater than the second number.
5. The device of claim 4 , wherein the first number equals a number of word lines activated one at a time during the refresh operation for the memory cells in the non-edge memory block.
6. The device of claim 1 , wherein the second number is greater than the first number.
7. The device of claim 6 , wherein the second number equals a number of word lines activated one at a time during the refresh operation for the memory cells in the non-edge memory block.
8. A semiconductor memory device, comprising: a memory cell array having at least one memory bank, the memory bank being divided into memory blocks such that the memory blocks have a block position including at least one edge memory block at an edge of the memory bank and at least one non-edge memory block, each memory block including a plurality of memory cells, each memory cell associated with at least one bit line and at least one word line; and a refresh execution circuit configured to activate a less than or equal number of word lines one at a time during a refresh operation for the memory cells in the edge memory block as activated one at a time during a refresh operation for the memory cells in the non-edge memory block, the refresh executing circuit including, a cell block position decision circuit configured to determine whether the refresh operation is for the at least one edge memory block or the at least one non-edge memory block based on a refresh address, and to output a cell block position decision signal based on the determination; a counter configured to receive refresh pulses and to count the refresh pulses based on the cell block position decision signal, and configured to output a count based on counting the refresh pulses; a multiplexer configured to output one of the count and the refresh pulses based on the cell block position decision signal; and a refresh counting circuit including a plurality of binary counters configured to generate the refresh address based on an output of the multiplexer.
9. The device of claim 8 , wherein the counter is enabled if the refresh address is for the at least one edge memory block, and disabled if the refresh address is for the at least one non-edge memory block.
10. The device of claim 8 , wherein the cell block position decision circuit is configured to perform a logical OR operation on at least a portion of outputs from the plurality of binary counters to generate the cell block position decision signal.
11. The device of claim 1 , wherein the memory cell array has an open bit line structure.
12. A refresh execution circuit configured to perform a refresh operation in a semiconductor memory device having a memory cell array, the memory cell including at least one memory bank having an at least one edge memory block at an edge of the memory bank and an at least one non-edge memory block, each memory block including a plurality of memory cells, each memory cell associated with at least one bit line and at least one word line, the refresh execution circuit comprising: a cell block position decision circuit configured to determine whether the refresh operation is for the at least one edge memory block or the at least one non-edge memory block based on a refresh address, and to output a cell block position decision signal based on the determination of the block position; a counter configured to receive refresh pulses and to count the refresh pulses based on the cell block position decision signal, and configured to output a count based on counting the refresh pulses; a multiplexer configured to output one of the count and the refresh pulses based on the cell block position decision signal; and a refresh counting circuit including a plurality of binary counters configured to generate the refresh address based on an output of the multiplexer.
13. The device of claim 12 , wherein the counter is configured to output the count if the refresh address is for the at least one edge memory block, and configured to output a no count if the refresh address is for the at least one non-edge memory block.
14. The device of claim 12 , wherein the cell block position decision circuit is configured to perform a logical OR operation on at least a portion of outputs from the plurality of binary counters, and configured to generate the cell block position decision signal.
15. The device of claim 12 , wherein the memory cell array has an open bit line structure.
16. A data processing system comprising: a main board; a central processing unit mounted on the main board; and a memory device electrically coupled to the central processing unit, the memory device having a memory cell array, the memory cell including at least one memory bank having an at least one edge memory block at an edge of the memory bank and an at least one non-edge memory block, each memory block including a plurality of memory cells, each memory cell associated with at least one bit line and at least one word line, wherein a less than or equal number of word lines one at a time during a refresh operation for the memory cells in the edge memory block as activated one at a time during a refresh operation for the memory cells in the non-edge memory block, wherein the at least one edge memory block is configured such that the refresh operation involves a plurality of word lines, and the memory device is configured to perform the refresh operation on the memory cells in the edge memory block in a first and second stage, and configured to activate a first number of the plurality of word lines one at a time in the first stage and to activate a second number of the plurality of word lines one at a time in the second stage, such that each of the plurality of word lines is activated during the refresh operation.
17. The data processing system of claim 16 , wherein the memory device is a volatile semiconductor memory device.
18. The data processing system of claim 16 , wherein the memory device is dynamic random access memory (DRAM).
19. The device of claim 8 , wherein the memory cell array has an open bit line structure.
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April 30, 2009
April 19, 2011
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