An integrated circuit that supports testing of multiple pads via a subset of these pads includes at least two sections. Each section has multiple pads and multiple test access circuits coupled to these pads. For each section, one pad is designated as a primary pad and the remaining pads are designated as secondary pads. For each section, the test access circuits couple the secondary pads to the primary pad such that all of the pads in the section can be tested by probing just the primary pad. Each test access circuit may be implemented with a simple switch. A controller generates a set of control signals for the test access circuits in all sections. These control signals enable and disable the test access circuits such that all of the sections can be tested in parallel, and the pads in each section can be tested in a sequential order.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An integrated circuit comprising: a plurality of input/output (I/O) circuits; a plurality of pads, each pad coupled to a corresponding one of the plurality of I/O circuits; a plurality of test access circuits each coupled to a corresponding one of the plurality of pads and to a corresponding one of the plurality of I/O circuits; a common connection node coupled to each of the plurality of test access circuits, wherein the common connection node, plurality of test access circuits and plurality of pads are configured so there is a test access circuit between each pad and the common connection node, and two access circuits and the common connection node between each one of the plurality of pads and every other one of the plurality of pads; and a controller coupled to each of the plurality of test access circuits, the controller configured to send control signals to each of the plurality of test access circuits to selectively enable one or more of the test access circuits, wherein the controller is configured to generate the control signals in a manner that individually enables test access circuits to connect the corresponding I/O circuit to a test signal applied to one of the plurality of pads (primary pad), thereby enabling testing each of the plurality of I/O circuits by directly probing only the primary pad and not directly applying a test probe to any of the other of the plurality of pads (secondary pads).
2. The integrated circuit of claim 1 , wherein the plurality of test access circuits are configured such that the primary pad is tested by a control signal from the controller disabling a test access circuit corresponding to the primary pad.
3. The integrated circuit of claim 2 , wherein the plurality of test access circuits are further configured such that each secondary pad is tested by control signals from the controller enabling the one of the plurality of test access circuits corresponding to the primary pad, enabling the one of the plurality of test access circuits corresponding to the secondary pad being tested, and disabling all other test access circuits.
4. The integrated circuit of claim 2 , wherein each test access circuit among the plurality of test access circuits comprises a switch coupled between the common connection node and the corresponding one of the plurality of pads associated with the test access circuit.
5. The integrated circuit of claim 4 , wherein the switch of each test access circuit comprises at least one field effect transistor (FET).
6. The integrated circuit of claim 1 , wherein the primary pad is further configured to receive a test signal for direct current (DC) testing or slow alternating current (AC) testing of the plurality of pads.
7. The integrated circuit of claim 1 , wherein the controller is operative to generate the control signals to test the plurality of pads in a sequential order.
8. The integrated circuit of claim 1 , wherein the plurality of test access circuits are fabricated with complementary metal oxide semiconductor (CMOS).
9. An integrated circuit comprising: at least two sections, each section comprising: a plurality of input/output (I/O) circuits; a plurality of pads, each pad coupled to a corresponding one of the plurality of I/O circuits; a plurality of test access circuits each coupled to a corresponding one of the plurality of pads and to a corresponding one of the plurality of I/O circuits; a common connection node coupled to each of the plurality of test access circuits, wherein the common connection node, plurality of test access circuits and plurality of pads are configured so there is a test access circuit between each pad and the common connection node, and two access circuits and the common connection node between each one of the plurality of pads and every other one of the plurality of pads; and a controller coupled to each section and to each of the plurality of test access circuits, the controller configured to send control signals to each of the plurality of test access circuits to selectively enable one or more of the test access circuits, wherein the controller is configured to generate the control signals in a manner that individually enables test access circuits in each section to connect the corresponding I/O circuits to a test signal applied to one of the plurality of pads in each section (primary pad), thereby enabling testing each of the plurality of I/O circuits by directly probing only the primary pads and not directly applying a test probe to any of the other of the plurality of pads (secondary pads).
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 12, 2010
April 26, 2011
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