The semiconductor storage apparatus includes a memory cell array including memory cells each having a rectifying element and a variable resistive element connected in series, the memory cells being arranged in crossing portions of a plurality of first wires and a plurality of second wires, and a control circuit configured to control charging to the first wire. The control circuit charges the first wire connected to a selected memory cell up to a first potential, and then set the first wire in a floating state. Then it charges another first wire adjacent to the first wire connected to the selected memory cell to a second potential. The potential of the first wire connected to the selected memory cell is thereby caused to rise to a third potential by coupling.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor storage apparatus, comprising: a memory cell array including memory cells each having a rectifying element and a variable resistive element connected in series, the memory cells being arranged in crossing portions of a plurality of first wires and a plurality of second wires; and a control circuit configured to control charging to the first wire, the control circuit being configured to sequentially perform a first step to charge the first wire connected to a selected memory cell up to a first potential and then set the first wire in floating state, and then a second step to charge another first wire adjacent to the first wire connected to the selected memory cell up to a second potential, thereby causing the potential of the first wire connected to the selected memory cell to rise up to a third potential by coupling, data program of the selected memory cell being performed by the third potential.
2. The semiconductor storage apparatus according to claim 1 , further comprising a selection transistor connected to the first wire and having a gate supplied with a selection signal, wherein the selection transistor is configured to turn off, when the first wire is charged up to a potential controlled by a magnitude of the selection signal, to maintain the first wire in a floating state.
3. The semiconductor storage apparatus according to claim 2 , wherein after another first wire adjacent to the first wire connected to the selected memory cell is charged to the second potential, the control circuit performs an operation to lower a gate signal of the selection transistor connected to the first wire connected to the selected memory cell.
4. The semiconductor storage apparatus according to claim 3 , wherein after another first wire adjacent to the first wire connected to the selected memory cell is charged to the second potential, the control circuit performs the operation to lower the gate signal of the selection transistor connected to another first wire adjacent to the first wire connected to the selected memory cell.
5. The semiconductor storage apparatus according to claim 1 , wherein another first wire which is adjacent to the first wire connected to the selected memory cell and is charged to the second potential is not connected to a memory cell for which set operation to change from a high-resistance state to a low-resistance state is completed.
6. The semiconductor storage apparatus according to claim 1 , wherein the memory cell array includes a plurality of memory mats arranged along the same direction as that of the first wire, the first wire is shared by two of the memory cell mats adjacent to each other, and the first wires adjacent to each other in one of the memory cell mats are pulled out therefrom in opposite directions.
7. The semiconductor storage apparatus according to claim 6 , wherein when the first wire connected to the selected memory cell is shared by the (n+1)-th (n is a natural number) and (n+2)-th memory mats, the control circuit charges the first wire shared by the n-th and (n+1)-th memory mats up to the second potential and also charges the first wire shared by the (n+2)-th and (n+3)-th memory mats up to a potential that is different from the second potential.
8. The semiconductor storage apparatus according to claim 6 , wherein the first wire charged up to the second potential does not extend to a memory mat including the selected memory cell, and is adjacent to the first wire connected to the selected memory cell in a memory mat adjacent to the memory mat including the selected memory cell.
9. The semiconductor storage apparatus according to claim 8 , wherein the first wires charged up to the second potential are adjacent to the first wire connected to the selected memory cell on both sides thereof.
10. The semiconductor storage apparatus according to claim 1 , wherein the control circuit is configured to perform a third step that charges the second wire crossing the first wire up to a fourth potential between the first step and the second step, thereby raising by coupling the potential of the first wire connected to the selected memory cell up to a fifth potential lower than the third potential.
11. The semiconductor storage apparatus according to claim 10 , wherein the control circuit is configured to perform a fourth step that charges the second wire crossing the first wire up to a sixth potential before the first step, the sixth potential is lower than the fourth potential.
12. A semiconductor storage apparatus comprising: a memory cell array including a memory cells each having rectifying element and a variable resistive element connected in series, the memory cells being arranged in crossing portions of a plurality of first wires and a plurality of second wires; a selection transistor connected to the first wire and having a gate supplied with a selection signal; and a control circuit configured to control charging to the first wire by controlling the selection transistor, the control circuit being configured to control the selection signal to be supplied to the selection transistor that is connected to the first wire connected to the selected memory cell to charge the first wire to a first potential and then set the first wire in a floating state by lowering a magnitude of the selection signal.
13. A data programming method of a semiconductor storage apparatus having a memory cell array including memory cells each having a rectifying element and a variable resistive element connected in series, the memory cells being arranged in crossing portions of a plurality of first wires and a plurality of second wires, the method comprising: after charging the first wire connected to the selected memory cell up to a first potential, setting the first wire connected to the selected memory cell in a floating state; charging another first wire adjacent to the first wire connected to the selected memory cell up to a second potential, thereby causing the potential of the first wire connected to the selected memory cell to rise up to a third potential by coupling; and performing data program of the selected memory cell by the third potential.
14. The data program method of a semiconductor storage apparatus according to claim 13 , wherein the semiconductor storage apparatus further comprises a selection transistor connected to the first wire and having a gate supplied with a selection signal and the selection transistor is configured to turn off, when the first wire is charged up to a potential controlled by a magnitude of the selection signal, to maintain the first wire in a floating state.
15. The data program method of a semiconductor storage apparatus according to claim 14 , wherein after another first wire adjacent to the first wire connected to the selected memory cell is charged to the second potential, an operation to lower a gate signal of the selection transistor connected to the first wire connected to the selected memory cell is performed.
16. The data program method of a semiconductor storage apparatus according to claim 13 , wherein another first wire which is adjacent to the first wire connected to the selected memory cell and is charged to the second potential is not connected to a memory cell for which set operation to change from a high-resistance state to a low-resistance state is completed.
17. The data program method of a semiconductor storage apparatus according to claim 13 , wherein the memory cell array includes a plurality of memory mats arranged along the same direction as that of the first wire, the first wire is shared by two of the memory cell mats adjacent to each other, and the first wires adjacent to each other in one of the memory cell mats are pulled out in opposite directions.
18. The data program method of a semiconductor storage apparatus according to claim 17 , wherein when the first wire connected to the selected memory cell is shared by the (n+1)-th (n is a natural number) and (n+2)-th memory mats, the first wire shared by the n-th and (n+1)-th memory mats is charged up to the second potential and also the first wire shared by the (n+2)-th and (n+3)-th memory mats is charged up to a potential that is different from the second potential.
19. The data program method of a semiconductor storage apparatus according to claim 17 , wherein the first wire charged up to the second potential does not extend to a memory mat including the selected memory cell, and is adjacent to the first wire connected to the selected memory cell in a memory mat adjacent to the memory mat including the selected memory cell.
20. The data program method of a semiconductor storage apparatus according to claim 13 , wherein the second wire crossing first wire is charged up to a fourth potential after the first wire is set in a floating state and before the another first wire adjacent to the first wire connected to the selected memory cell is charged up to the second potential, thereby raising by coupling the potential of the first wire connected to the selected memory cell up to a fifth potential lower than the third potential.
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August 20, 2009
May 3, 2011
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