Parallel bit test apparatus and parallel bit test method capable of reducing test time

1. A parallel bit test (PBT) apparatus included in memory chips that are stacked in a multi-chip package (MCP) and share a set of data signal lines, the PBT apparatus comprising: a comparing unit configured to output a representative data signal that is representative of a comparison between test data signals provided to a given one of the memory chips and corresponding data signals output therefrom, respectively; and a coding unit configured to output the representative data signal using a first subset of the shared set of data signal lines, the first subset not overlapping other subsets used by coding units corresponding to the other ones of the memory chips, respectively, the coding unit selecting one or more of the data signal lines amongst the shared set of data signal lines for inclusion in the first subset according to a first test mode register set (MRS) signal wherein a plurality of the memory chips simultaneously output respective representative data using the respective non-overlapping subsets of the shared data signal lines.

2. The PBT apparatus as claimed in claim 1 , wherein the first test MRS signal controls the representative data signals to be outputted via the first subset by changing a path through which a representative data signal, inputted to the coding unit, is outputted.

3. The PBT apparatus as claimed in claim 2 , wherein the first test MRS signal is set and inputted by a user.

4. The PBT apparatus as claimed in claim 3 , further comprising a buffer unit to buffer and then output the representative data signal outputted from the coding unit.

5. The PBT apparatus as claimed in claim 4 , further comprising a driver to receive an input signal outputted from the buffer unit, and to drive and output the received signal onto a data signal line designated by the first test MRS signal.

6. The PBT apparatus as claimed in claim 3 , wherein the comparing unit includes 1 through n comparators when 2n input data is inputted, and the number of representative data signals outputted is determined based on the number of comparators included.

7. The PBT apparatus as claimed in claim 6 , wherein the comparing unit outputs 2n−1 representative data signals when k comparators are included, the comparators being connected in series and an output signal of the previous comparator being an input signal of the next comparator, wherein k and n are integers, and 1≦k≦n.

8. The PBT apparatus as claimed in claim 7 , wherein each comparator compares and determines whether received data signals are the same using OR gates, and 2 k-1 OR gates are included when 2 k data signals are inputted to the corresponding comparator.

9. The PBT apparatus as claimed in claim 8 , wherein: the comparing unit includes five comparators connected in series; a first one of the comparators disposed first in the series receives a 32 bit data signal and a fifth one of the comparators disposed fifth in the series outputs a 1 bit representative data signal, the first comparator includes 16 OR gates which logically OR the data signals, and outputs 16 signals to an input terminal of a second one of the comparators; and the fifth comparator includes one OR gate which logically ORs an output signal received from a fourth one of the comparators connected thereto, an output of the one OR gate being the 1 bit representative data signal.

10. The PBT apparatus as claimed in claim 8 , wherein: the comparing unit includes four comparators connected in series; a first one of the comparators disposed first in the series receives a 32 bit data signal and a fourth one of the comparators disposed fourth in the series outputs a 2 bit representative data signal, the first comparator includes 16 OR gates which logically OR the data signals, and outputs 16 signals to an input terminal of a second one of the comparators, and the fourth comparator includes one OR gate which logically ORs an output signal received from a third one of the comparators connected thereto, an output of the one OR gate being the 2 bit representative data signal.

11. The PBT apparatus as claimed in claim 1 , wherein each PBT apparatus is activated when a second test MRS signal representing a command to perform a PBT is applied to the memory chips for simultaneously testing the memory chips, and the second test MRS signal is set and inputted by the user.

12. The PBT apparatus as claimed in claim 1 , further comprising an input signal processor, positioned prior to the comparing unit and including at least one bit line sense amplifier, to output an inversion signal and a non-inversion signal, wherein the comparing unit receives the non-inversion signal outputted from the input signal processor.

13. A parallel bit test (PBT) method which simultaneously tests memory chips stacked in a multi-chip package (MCP), the memory chips sharing a set of data signal lines, the PBT method comprising: receiving a command to perform a PBT on the memory chips; outputting representative data signals that represent comparisons between groups of test data signals provided to the memory chips and corresponding groups of data signals output therefrom, respectively; selecting non-overlapping subsets of the one or more of the data signal lines amongst the shared set of data signal lines, the non-overlapping subsets corresponding to the memory chips, respectively; and simultaneously outputting the representative data signals via the non-overlapping subsets of data signal lines, respectively.

14. The PBT method as claimed in claim 13 , wherein the first test MRS signal controls the representative data signals to be outputted to the different data signal lines by changing a path through which the representative data signal, outputted from the memory chip, is outputted.

15. The PBT method as claimed in claim 14 , wherein the first test MRS signal is set and inputted by a user.

16. The PBT method as claimed in claim 14 , wherein the inputting of the command comprises: inputting the command to all memory chips; and selecting all memory chips to be parallel bit tested by applying a memory chip selecting signal to all memory chips.

17. The PBT method as claimed in claim 14 , wherein in the performing of the PBT and the outputting of the representative data signal, the input data signals are compared and sameness thereof is determined using OR gates.

18. A multi-chip package (MCP), comprising: memory chips that share a plurality of data signal lines; and a plurality of parallel bit test (PBT) apparatuses at least associated with the memory chips, respectively; each of the PBT apparatuses including: a comparing unit configured to output a representative data signal that is representative of a comparison between test data signals provided to an associated one of the memory chips and corresponding data signals output therefrom, respectively; and a coding unit configured to output the representative data signal using a first subset of the shared set of data signal lines, the first subset not overlapping other subsets used by coding units corresponding to the other ones of the memory chips, respectively, the coding unit selecting one or more of the data signal lines amongst the shared set of data signal lines for inclusion in the first subset according to a first test mode register set (MRS) signal, wherein a plurality of the memory chips simultaneously output respective representative data using the respective non-overlapping subsets of the shared data signal lines.

19. The MCP as claimed in claim 18 , wherein there is a 1:1 ratio between the memory chips and the PBT apparatuses.

20. The MCP as claimed in claim 18 , wherein the first test MRS signal controls the representative data signals to be outputted via the first subset of the shared set of data signal lines by changing a path through which a representative data signal, inputted to the coding unit, is outputted.