In a pattern layout which includes a first device pattern having a uniformly repeated pattern group having first lines and first spaces formed parallel to one anther and uniformly arranged with constant width at a constant pitch and a non-uniformly repeated pattern group having first lines and first spaces non-uniformly arranged, and a second device pattern arranged adjacent to the end portion of the non-uniformly repeated pattern group in an arrangement direction thereof and having second lines and second spaces whose widths are larger than the widths of the first lines and first spaces of the non-uniformly repeated pattern group, at least part of the widths of the first lines and the first spaces of the non-uniformly repeated pattern group is made larger than the width of the first line or the width of the first space of the uniformly repeated pattern group.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A pattern layout of an integrated circuit comprising: a first device pattern having a uniformly repeated pattern group having first lines and first spaces formed in a direction parallel to one another and uniformly and repeatedly arranged with constant width at a pitch with a constant interval and a non-uniformly repeated pattern group having first lines and first spaces non-uniformly and repeatedly arranged, the non-uniformly repeated pattern group being positioned adjacent to an end portion of the uniformly repeated pattern group and in the parallel direction, and a second device pattern arranged adjacent to the non-uniformly repeated pattern group and opposite to the uniformly repeated pattern group with respect to the non-uniformly repeated pattern group, arranged in parallel to the first device pattern and having second lines and second spaces whose widths are larger than widths of the first lines and first spaces of the non-uniformly repeated pattern group, wherein at least part of the widths of the first lines and the first spaces of the non-uniformly repeated pattern group in the first device pattern is made larger than one of the width of the first line and the width of the first space of the uniformly repeated pattern group.
2. The pattern layout of the integrated circuit according to claim 1 , wherein the width of the second line is not smaller than twice the width of the first line of the uniformly repeated pattern group and the width of the second space is not smaller than twice the width of the first space of the uniformly repeated pattern group.
3. The pattern layout of the integrated circuit according to claim 1 , wherein at least part of the width of the first line and the width of the first space of the uniformly repeated pattern group is increased to set equal optical image strengths in the non-uniformly repeated pattern group and uniformly repeated pattern group.
4. The pattern layout of the integrated circuit according to claim 1 , wherein constant width of the uniformly repeated pattern group of the first device pattern is minimum dimension of lithography and the first lines of the non-uniformly repeated pattern group are arranged on both ends of the first device pattern.
5. The pattern layout of the integrated circuit according to claim 4 , wherein the second lines and second spaces of the second device pattern have dimensions not smaller than twice the minimum dimension and the second spaces are arranged on both ends thereof.
6. The pattern layout of the integrated circuit according to claim 1 , wherein the first device pattern corresponds to control gate wires of a memory cell portion of a NAND flash memory and the second device pattern corresponds to selection gate wires of the flash memory.
7. A NAND flash memory comprising: a control gate pattern having a uniformly repeated pattern group having first lines and first spaces formed in a direction parallel to one another and uniformly and repeatedly arranged with constant width at a pitch with a constant interval and a non-uniformly repeated pattern group having first lines and first spaces non-uniformly and repeatedly arranged, the non-uniformly repeated pattern group being positioned adjacent to an end portion of the uniformly repeated pattern group and in the parallel direction, and a selection gate pattern arranged adjacent to the non-uniformly repeated pattern group and opposite to the uniformly repeated pattern group with respect to the non-uniformly repeated pattern group, arranged in parallel to the control gate pattern and having second lines and second spaces whose widths are larger than widths of the first lines and first spaces of the non-uniformly repeated pattern group, wherein at least part of the widths of the first lines and the first spaces of the non-uniformly repeated pattern group in the control gate pattern is made larger than one of the width of the first line and the width of the first space of the uniformly repeated pattern group.
8. The NAND flash memory according to claim 7 , wherein the width of the second line is not smaller than twice the width of the first line of the uniformly repeated pattern group and the width of the second space is not smaller than twice the width of the first space of the uniformly repeated pattern group.
9. The NAND flash memory according to claim 7 , wherein at least part of the width of the first line and the width of the first space of the non-uniformly repeated pattern group is increased to set equal optical image strengths in the non-uniformly repeated pattern group and uniformly repeated pattern group.
10. The NAND flash memory according to claim 7 , wherein constant width in the uniformly repeated pattern group of the control gate pattern is minimum dimension of lithography and the first lines of the non-uniformly repeated pattern group are arranged on both ends of the control gate pattern.
11. The NAND flash memory according to claim 10 , wherein the second lines and second spaces of the selection gate pattern have dimensions not smaller than twice the minimum dimension and the second spaces are arranged on both ends thereof.
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November 21, 2007
May 10, 2011
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