A method of fabricating a strained silicon transistor is provided. Amorphous silicon is formed below the transistor region before the transistor is formed. By using the tensile/compressive strainer, amorphous silicon is recrystallized to form a strained silicon layer. In addition, the dopants in the well can be driven in and activated by using the same annealing process with the amorphous silicon recrystallization.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of fabricating a strained silicon transistor, comprising: providing a substrate comprising a first transistor region, a second transistor region and an insulator disposed between said first transistor region and said second transistor region; forming a first strained silicon layer in said substrate within said first transistor region, wherein forming said first strained silicon layer comprises: performing an amorphous silicon procedure within said first transistor region; forming a first strained layer to cover said first transistor region; performing a first annealing procedure to form said first strained silicon layer in said substrate within said first transistor region; and removing said first strained layer; and forming a transistor of a first conductivity type on said first strained silicon layer.
2. The method of claim 1 , wherein forming said second first strained silicon layer comprises: performing a amorphous silicon procedure within said second transistor region; forming a second strained layer to cover said second transistor region; performing a first annealing procedure to form said second strained silicon layer in said substrate within said second transistor region; and removing said second strained layer.
3. The method of claim 2 , wherein said first conductivity type is N-type and said second conductivity type is P-type.
4. The method of claim 2 , wherein after removing said first strained layer and said second strained layer and before forming said transistor the method further comprises: forming a first doped well within said first transistor region; forming a second doped well within said second transistor region; and performing a second annealing procedure to activate dopants in said first doped well and in second doped well.
5. The method of claim 2 , wherein said first strained layer and said second strained layer respectively comprise silicon nitride.
6. The method of claim 2 , wherein said first strained layer and said second strained layer respectively comprise a structure of a bottom layer being silicon oxide and of a top layer being silicon nitride.
7. The method of claim 2 , wherein said first strained layer has a tensile strain and said second strained layer has a compressive strain.
8. The method of claim 2 , wherein said amorphous silicon procedure is an ion implantation procedure and said ion implantation procedure comprises using Xe, Ar and Ge ions.
9. The method of claim 1 , further comprising: forming a second strained silicon layer in said substrate within said second transistor region; and forming a transistor of a second conductivity type on said second strained silicon layer.
10. A method of fabricating a strained silicon transistor, comprising: providing a substrate comprising a first transistor region, a second transistor region and an insulator disposed between said first transistor region and said second transistor region; forming a first strained silicon layer in said substrate within said first transistor region, wherein the step of forming said first strained silicon layer comprises: forming a first doped well within said first transistor region; performing a first amorphous silicon procedure within said first transistor region; forming a first strained layer to cover said first transistor region; performing an annealing procedure to form said first strained silicon layer and to drive and to activate dopants in said first doped well; and removing said first strained layer; and forming a transistor of a first conductivity type on said first strained silicon layer.
11. The method of claim 10 , wherein said amorphous silicon procedures are performed after said doped wells are formed.
12. The method of claim 10 , wherein said doped wells are formed after said amorphous silicon procedures are performed.
13. The method of claim 10 , wherein the step of forming said second strained silicon layer comprises: forming a second doped well within said second transistor region; performing a second amorphous silicon procedure within said second transistor region; forming a second strained layer to cover said second transistor region; and performing said annealing procedure to form said second strained silicon layer and to drive and to activate dopants in said second doped well; and removing said second strained layer.
14. The method of claim 13 , wherein said first strained layer and said second strained layer respectively comprise silicon nitride.
15. The method of claim 13 , wherein said first strained layer and said second strained layer respectively comprise a structure of a bottom layer being silicon oxide and of a top layer being silicon nitride.
16. The method of claim 13 , wherein said first strained layer has a tensile strain and said second strained layer has a compressive strain.
17. The method of claim 13 , wherein said first amorphous silicon procedure and said second amorphous silicon procedure respectively comprise an ion implantation procedure using Xe, Ar and Ge ions.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 20, 2008
May 31, 2011
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.