A element group includes a plurality of semiconductor elements stacked in a step-like shape on a wiring board. The semiconductor elements are electrically connect to connection pads of the wiring board through metal wires. Among the plural semiconductor elements stacked in a step-like shape, the uppermost semiconductor element has a thickness larger than that of the semiconductor element immediately below it.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device, comprising: a wiring board having a first surface provided with external connection terminals and a second surface provided with an element mounting section and connection pads; a first element group provided with a plurality of first semiconductor elements having first electrode pads arranged along one outline side, the first semiconductor elements being stacked in a step shape on the element mounting section of the wiring board with the outline sides directed to the same direction and the first electrode pads exposed; a second element group provided with a plurality of second semiconductor elements having second electrode pads arranged along one outline side, the second semiconductor elements being stacked in a step shape on the first element group in a direction opposite to the stepped direction of the first element group with the outline sides directed to the same direction and the electrode pads exposed; metal wires electrically connecting the first and second electrode pads of the first and second semiconductor elements and the connection pads of the wiring board; and a sealing resin layer formed on the second surface of the wiring board to seal the first and second element group together with the metal wires, wherein the second element group satisfies conditions T 1 =1.1TA to 1.5TA, T 2 =2.5TA to 3.5TA, where a thickness of the uppermost second semiconductor element in the second element group is T 1 , a thickness of the lowermost second semiconductor element in the second element group is T 2 , and a thickness of the other second semiconductor elements in the second element group is TA.
2. The semiconductor device according to claim 1 , wherein the first element group satisfies a condition T 3 =1.5TB to 2.5TB, where a thickness of the lowermost first semiconductor element in the first element group is T 3 , and a thickness of the other first semiconductor elements in the first element group is TB.
3. The semiconductor device according to claim 1 , wherein the thickness TA of the other second semiconductor elements are in a range of 10 to 50 μm.
4. The semiconductor device according to claim 1 , wherein the first and second element group is provided with a plurality of memory elements as the first and second semiconductor elements.
5. The semiconductor device according to claim 4 , further comprising: a controller element, stacked on the second element group, having electrode pads arranged along a outline side.
6. The semiconductor device according to claim 5 , wherein the electrode pads of the controller element are electrically connected to the connection pads of the wiring board via metal wires.
7. A semiconductor device, comprising: a wiring board having a first surface provided with external connection terminals and a second surface provided with an element mounting section and connection pads; an element group, mounted on the element mounting section of the wiring board, including at least one semiconductor element having electrode pads arranged along a outline side; metal wires electrically connecting the connection pads of the wiring board and the electrode pads of the semiconductor element; a sealing resin layer formed on the second surface of the wiring board to seal the element group together with the metal wires; and a slope portion formed on ends of the wiring board and the sealing resin layer ranging from the first surface of the wiring board to the sealing resin layer, wherein the semiconductor element is arranged on the wiring board via a dummy element having a size which fits in an outer shape of the wiring board, and an end of the semiconductor element is protruded from the end of the wiring board to locate above the slope portion.
8. The semiconductor device according to claim 7 , wherein the dummy element has a thickness that the slope portion does not interfere with the semiconductor element.
9. A semiconductor device, comprising: a wiring board having a first surface provided with external connection terminals and a second surface provided with an element mounting section and connection pads; an element group, mounted on the element mounting section of the wiring board, including at least one semiconductor element having electrode pads arranged along a outline side; metal wires electrically connecting the connection pads of the wiring board and the electrode pads of the semiconductor element; a sealing resin layer formed on the second surface of the wiring board to seal the element group together with the metal wires; and a slope portion formed on ends of the wiring board and the sealing resin layer ranging from the first surface of the wiring board to the sealing resin layer, wherein the semiconductor element is arranged on the wiring board via an adhesive layer having an incline corresponding to the slope portion, and an end of the semiconductor element is protruded from the end of the wiring board to locate above the slope portion.
10. The semiconductor device according to claim 9 , wherein the adhesive layer has a thickness that the slope portion does not interfere with the semiconductor element.
11. A semiconductor device, comprising: a wiring board having a first surface provided with external connection terminals and a second surface provided with an element mounting section and connection pads; an element group, mounted on the element mounting section of the wiring board, including at least one semiconductor element having electrode pads arranged along a outline side; metal wires electrically connecting the connection pads of the wiring board and the electrode pads of the semiconductor element; a sealing resin layer formed on the second surface of the wiring board to seal the element group together with the metal wires; and a slope portion formed on ends of the wiring board and the sealing resin layer ranging from the first surface of the wiring board to the sealing resin layer, wherein the semiconductor element has an incline corresponding to the slope portion, and an end of the semiconductor element is protruded from the end of the wiring board to locate above the slope portion.
12. The semiconductor device according to claim 11 , wherein the semiconductor element has a thickness that the incline does not interfere with a circuit portion provided on the semiconductor element.
13. The semiconductor device according to claim 11 , wherein the element group is provided with a plurality of the semiconductor elements, and the lowermost semiconductor element among the semiconductor elements has the incline.
14. A semiconductor device, comprising: a wiring board having a first surface provided with external connection terminals and a second surface provided with an element mounting section and connection pads; an element group provided with a plurality of semiconductor elements having electrode pads arranged along one outline side, the semiconductor elements being stacked in a step shape displaced to one direction on the element mounting section of the wiring board with the outline sides directed to the same direction and the electrode pads exposed; metal wires electrically connecting the electrode pads of the semiconductor elements and the connection pads of the wiring board; and a sealing resin layer formed on the second surface of the wiring board to seal the element group together with the metal wires, wherein the element group satisfies conditions T 1 =1.1T to 1.5T, T 2 =2.5T to 3.5T, where a thickness of the uppermost semiconductor element in the element group is T 1 , a thickness of the lowermost semiconductor element in the element group is T 2 , and a thickness of the other semiconductor elements in the element group is T.
15. The semiconductor device according to claim 14 , wherein the thickness T of the other semiconductor elements are in a range of 10 to 50 μm.
16. The semiconductor device according to claim 14 , wherein the element group is provided with a plurality of memory elements as the semiconductor elements.
17. The semiconductor device according to claim 16 , further comprising: a controller element, stacked on the element group, having electrode pads arranged along an outline side.
18. The semiconductor device according to claim 17 , wherein the electrode pads of the controller element are electrically connected to the connection pads of the wiring board via metal wires.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 28, 2008
May 31, 2011
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