Memory element, memory apparatus, and semiconductor integrated circuit

1. A memory element comprising: a first electrode; a second electrode; and a resistance variable film which is disposed between the first and second electrodes to be connected to the first and second electrodes, a resistance value of the resistance variable film varying based on a voltage applied between the first and second electrodes, wherein the resistance variable film includes a layer made of Fe 3 O 4 and a layer made of Fe 2 O 3 or a spinel structure oxide which is expressed as MFe 2 O 4 (M: metal element except for Fe), and wherein the layer made of Fe 3 O 4 is thicker than the layer made of Fe 2 O 3 or the spinel structure oxide.

2. The nonvolatile memory element according to claim 1 , wherein the layer made of Fe 2 O 3 or the spinel structure oxide is formed at least either in the vicinity of an interface between the resistance variable film and the first electrode or in the vicinity of an interface between the resistance variable film and the second electrode.

3. The memory element according to claim 1 , wherein the resistance variable film has a thickness that is not smaller than 1 nm and not larger than 200 nm.

4. The memory element according to claim 1 , wherein the layer made of Fe 2 O 3 or the spinel structure oxide has a thickness that is not larger than 20% of a thickness of the resistance variable film.

5. The memory element according to claim 1 , wherein M of the spinel structure oxide is at least one element selected from a group consisting of Mn, Co, Ni, Cu, and Zn.

6. The memory element according to claim 1 , wherein at least one of the first and second electrodes is made of a material selected from a group consisting of Ag, Au, Pt, Ru, RuO 2 , Ir, IrO 2 , TiO, TiN, and TiAlN.

7. The memory element according to claim 1 , wherein a predetermined pulse voltage is applied between the first electrode and the second electrode to cause 1-bit or multi-bit data to be stored therein according to a variation in the resistance value.

8. The memory element according to claim 1 , wherein a predetermined voltage is applied between the first electrode and the second electrode to cause 1-bit or multi-bit data to be reproduced so as to correspond to a current value according to a variation in the resistance value.

9. A memory element comprising: a memory array including: a semiconductor substrate; a plurality of first electrode wires formed on the semiconductor substrate to extend in parallel with each other; a plurality of second electrode wires formed above the plurality of first electrode wires so as to extend in parallel with each other within a plane parallel to a main surface of the semiconductor substrate and so as to three-dimensionally cross the plurality of first electrode wires; and nonvolatile memory elements provided to respectively correspond to three-dimensional cross points between the plurality of first electrode wires and the plurality of second electrode wires, wherein: each of the nonvolatile memory elements includes a resistance variable film which is disposed between the first and second electrode wires, a resistance value of the resistance variable film varying based on a voltage applied between the first and second electrode wires; the resistance variable film includes a layer made of Fe 3 O 4 and a layer made of Fe 2 O 3 or a spinel structure oxide which is expressed as MFe 2 O 4 (M: metal element except for Fe), and the layer made of Fe 3 O 4 is thicker than the layer made of Fe 2 O 3 or the spinel structure oxide.

10. The nonvolatile memory element according to claim 9 , wherein the layer made of Fe 2 O 3 or the spinel structure oxide is formed at least either in the vicinity of an interface between the resistance variable film and the first electrode wire or in the vicinity of an interface between the resistance variable film and the second electrode wire.

11. The memory element according to claim 9 , wherein the resistance variable film has a thickness that is not smaller than 1 nm and not larger than 200 nm.

12. The memory element according to claim 9 , wherein the layer made of Fe 2 O 3 or the spinel structure oxide has a thickness that is not larger than 20% of a thickness of the resistance variable film.

13. The memory element according to claim 9 , wherein M of the spinel structure oxide is at least one element selected from a group consisting of Mn, Co, Ni, Cu, and Zn.

14. The memory element according to claim 9 , wherein at least one of the first and second electrode wires is made of a material selected from a group consisting of Ag, Au, Pt, Ru, RuO 2 , Ir, IrO 2 , TiO, TiN, and TiAlN.

15. The memory element according to claim 9 , wherein a predetermined pulse voltage is applied between the first electrode wire and the second electrode wire to cause 1-bit or multi-bit data to be stored therein according to a variation in the resistance value.

16. The memory element according to claim 9 , wherein a predetermined voltage is applied between the first electrode wire and the second electrode wire to cause 1-bit or multi-bit data to be reproduced so as to correspond to a current value according to a variation in the resistance value.

17. A memory apparatus comprising: a plurality of word lines extending in a first direction; a plurality of bit lines extending in a second direction so as to cross the word lines; a plurality of plate lines extending in the second direction so as to respectively correspond to the plurality of bit lines; a plurality of transistors provided to respectively correspond to intersections between the word lines and the bit lines; a plurality of memory elements respectively corresponding to the plurality of transistors; a word line driving portion which is connected to the plurality of word lines and is configured to control voltage application to the word lines; and a bit line/plate line driving portion which is connected to the plurality of bit lines and to the plurality of plate lines and is configured to control voltage application to the bit lines and to the plate lines, wherein one of the plurality of transistors and one of the plurality of memory elements which is associated with the one of the plurality of transistors are connected in series between one of the plurality of bit lines and one of the plurality of plate lines which is associated with the one of the plurality of bit lines, wherein a gate of the one of the plurality of transistors is connected to one of the plurality of word lines and a drain and source of the one of the plurality of transistors is connected to the one of the bit lines and to the one of the memory elements, wherein the one of the memory elements includes a first electrode connected to the one of the plurality of transistors, a second electrode connected to the one of the plate lines, and a resistance variable film connected to the first electrode and to the second electrode, wherein the resistance variable film includes a layer made of Fe 3 O 4 and a layer made of Fe 2 O 3 or a spinel structure oxide which is expressed as MFe 2 O 4 (M: metal element except for Fe), and wherein the layer made of Fe 3 O 4 is thicker than the layer made of Fe 2 O 3 or the spinel structure oxide.

18. The memory apparatus according to claim 17 , wherein the word line driving portion is configured to apply an activation voltage to a word line connected to the gate of the transistor associated with the memory element in which predetermined data is to be stored to cause a drain-source of the transistor to be placed in an electrically conductive state, and wherein the bit line/plate line driving portion is configured to apply a first pulse voltage to a bit line connected to the transistor associated with the memory element in which the predetermined data is to be stored and to apply a second pulse voltage to a plate line associated with the bit line.

19. The memory apparatus according to claim 17 , wherein the word line driving portion is configured to apply an activation voltage to a word line connected to the gate of the transistor associated with the memory element from which prestored predetermined data is to be reproduced to cause a drain-source of the transistor to be placed in an electrically conductive state, and wherein the bit line/plate line driving portion is configured to apply a first reproducing voltage to a bit line connected to the transistor associated with the memory element from which the predetermined data is to be reproduced and to apply a second reproducing voltage to a plate line associated with the bit line.

20. A semiconductor integrated circuit comprising: a memory apparatus according to claim 17 ; and a logic circuit having a storing mode and a reproducing mode and being configured to execute predetermined calculation, wherein the logic circuit is configured to, in the storing mode, control the memory apparatus to cause the memory apparatus to store bit data therein, and is configured to, in the reproducing mode, control the memory apparatus to cause the memory apparatus to reproduce the bit data stored therein.

21. A semiconductor integrated circuit comprising: a a memory apparatus according to claim 17 ; and a processor having a program running mode and a program rewrite mode, wherein the processor is configured to, in the program running mode, run a program stored in the memory apparatus, and is configured to, in the program rewrite mode, rewrite the program stored in the memory apparatus to a program input externally.