A method of fabricating a semiconductor device includes: forming a first polysilicon layer having a first thickness in a peripheral circuit region formed on a substrate; forming a stack structure comprising a first tunneling insulating layer, a charge trap layer, and a blocking insulating layer in a memory cell region formed on the substrate; forming a second polysilicon layer having a second thickness that is less than the first thickness on the blocking insulating layer; and forming gate electrodes by siliciding the first and second polysilicon layers.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of fabricating a semiconductor device, the method comprising: forming a first polysilicon layer having a first thickness in a peripheral circuit region disposed on a substrate; forming a stack structure comprising a first tunneling insulating layer, a charge trap layer, and a blocking insulating layer in a memory cell region disposed on the substrate; forming a second polysilicon layer having a second thickness that is less than the first thickness on the blocking insulating layer; forming gate electrodes by siliciding the first and second polysilicon layers; forming a plurality of gate stack structures by patterning the second polysilicon layer, the blocking insulating layer, the charge trap layer, and the first tunneling insulating layer, which are formed in the memory cell region; forming a source/drain region by implanting an impurity into a surface of the substrate exposed to both sides of the plurality of gate stack structures; forming an oxide layer between each of the plurality of gate stack structures by performing an oxidation reaction over the substrate in which the plurality of gate stack structures are formed; and removing a portion of the oxide layer between each of the plurality of gate stack structures to a height at which the blocking insulating layer is formed.
2. The method of claim 1 , further comprising forming a second tunneling insulating layer in the peripheral circuit region of the substrate, wherein the forming of the first polysilicon layer comprises forming the first polysilicon layer on the second tunneling insulating layer.
3. The method of claim 2 , wherein the second tunneling insulating layer comprises SiO 2 .
4. The method of claim 2 , further comprising forming a p-channel metal oxide semiconductor (PMOS) transistor or a n-channel metal oxide semiconductor (NMOS) transistor in the peripheral circuit region according to the type of dopant doped into the second tunneling insulating layer.
5. The method of claim 1 , wherein the blocking insulating layer comprises a high-k dielectric material.
6. The method of claim 5 , wherein the blocking insulating layer comprises HfSixOy.
7. The method of claim 1 , wherein the forming of the gate electrodes comprises: forming a metal layer on the first and second polysilicon layers; and forming full silicide gate electrodes by a silicide reaction between the first and second polysilicon layers and the metal layer by heat-treating the metal layer.
8. The method of claim 7 , wherein the full silicide gate electrodes formed by the silicide reaction between the first polysilicon layer and the metal layer comprise monosilicide gate electrodes having the same contents of silicon and metal.
9. The method of claim 7 , wherein the full silicide gate electrodes formed by the silicide reaction between the second polysilicon layer and the metal layer comprise metal-rich silicide gate electrodes having a higher content of metal than of silicon.
10. The method of claim 7 , wherein the forming of the metal layer comprises forming the metal layer by simultaneously applying a metal material on the first and second polysilicon layers and the oxide layer.
11. The method of claim 10 , wherein the forming of the full silicide gate electrodes comprises: performing a first heat treatment on the substrate in which the metal layer is formed, at a first temperature so as to cause the silicide reaction between the metal layer and the first polysilicon layer and between the metal layer and the second polysilicon layer; removing a portion of the metal layer formed on the oxide layer, since the silicide reaction does not occur between the oxide layer and the portion of the metal layer formed on the oxide layer during the first heat treatment; and performing a second heat treatment on the substrate in which the portion of the metal formed on the oxide layer is removed, at a second temperature higher than the first temperature so that a first full silicide gate electrode is formed by the silicide reaction between the first polysilicon layer and the metal layer and a second full silicide gate electrode is formed by the silicide reaction between the second polysilicon layer and the metal layer, the first polysilicon layer being a monosilicide gate electrode and the second polysilicon layer being a metal-rich silicide gate electrode.
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July 27, 2009
June 28, 2011
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