A variable resistance memory device includes a memory cell connected to a bit line and a clamp circuit configured to provide either a first read voltage or a second read voltage to the bit line according to an elapsed time from a write operation of the memory cell. Related methods are also described.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A variable resistance memory device comprising: a memory cell connected to a bit line; and a clamp circuit configured to provide either a first read voltage or a second read voltage to the bit line according to an elapsed time from a write operation of the memory cell, wherein the first read voltage provided at a first elapsed time is lower than the second voltage provided at a second elapsed time longer than the first elapsed time.
2. The variable resistance memory device of claim 1 , wherein the first elapsed time corresponds to a verification read operation for the memory cell.
3. The variable resistance memory device of claim 1 , wherein when the memory cell is programmed to have a reset state, a first current generated by the first read voltage at the first elapsed time is same in size to a second current generated by the second read voltage at the second elapsed time.
4. A variable resistance memory device comprising: a memory cell connected to a bit line; and a clamp circuit configured to provide either a first read voltage or a second read voltage to the bit line according to an elapsed time from a write operation of the memory cell, wherein the memory cell comprises a variable resistance substance having a resistance value variable according a write current provided to the bit line; and a select element configured to switch in response to a selection signal provided via a word line.
5. The variable resistance memory device of claim 4 , wherein the variable resistance substance comprises a chalcogenide alloy.
6. A read method of a variable resistance memory device comprising: determining an elapsed time from a program time of a memory cell to a point of time when a read operation is conducted; and sensing data of the memory cell by variably providing a clamp voltage to clamp a bit line of the memory cell according to the elapsed time, wherein the determining comprises detecting whether an input command is a write command or a read command; and wherein the bit line is clamped to a first read voltage when the write command is detected and to a second read voltage higher than the first read voltage when the read command is detected.
7. The read method of claim 6 , wherein a verification read operation is conducted via a bit line clamped to the first read voltage.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 28, 2009
June 28, 2011
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.