Integrated circuit including gas phase deposited packaging material

1. An integrated circuit comprising: a semiconductor substrate including an active area on a frontside of the substrate; backside metal contacting a backside of the substrate, the backside of the substrate directly opposite the frontside of the substrate; and a gas phase deposited packaging material directly contacting and encapsulating the active area and directly contacting the backside metal, wherein the packaging material has a coefficient of thermal expansion between about 2-3 ppm/K.

2. The integrated circuit of claim 1 , further comprising: contacts contacting the active area and extending through the packaging material.

3. The integrated circuit of claim 1 , wherein the substrate comprises a thinned substrate.

4. The integrated circuit of claim 1 , wherein the packaging material comprises an amorphous inorganic or ceramic carbon.

5. The integrated circuit of claim 1 , wherein the packaging material has a thickness less than 100 μm.

6. A semiconductor wafer comprising: a semiconductor substrate including a plurality of dies, each die including an active area on a frontside of the substrate; backside metal contacting each die on a backside of the substrate, the backside of the substrate directly opposite the frontside of the substrate; and a gas phase deposited packaging material directly contacting and encapsulating the active area of each die, directly contacting the backside metal of each die, and providing sawing trenches between the dies, wherein the packaging material has a coefficient of thermal expansion between about 2-3 ppm/K.

7. The semiconductor wafer of claim 6 , wherein the substrate comprises a thinned substrate.

8. The semiconductor wafer of claim 6 , wherein the packaging material comprises an amorphous inorganic or ceramic carbon.

9. The semiconductor wafer of claim 6 , wherein the packaging material has a thickness less than 100 μm.

10. The semiconductor wafer of claim 6 , wherein the packaging material has a melting temperature above 370° C.

11. An integrated circuit comprising: a semiconductor substrate including an active area on a frontside of the substrate; backside metal contacting a backside of the substrate, the backside of the substrate directly opposite the frontside of the substrate; and a gas phase deposited packaging material directly contacting and encapsulating the active area and directly contacting the backside metal, wherein the packaging material is an amorphous inorganic or ceramic carbon.

12. The integrated circuit of claim 11 , further comprising: contacts contacting the active area and extending through the packaging material.

13. The integrated circuit of claim 11 , wherein the substrate comprises a thinned substrate.

14. The integrated circuit of claim 11 , wherein the packaging material has a thickness less than 100 μm.

15. A semiconductor wafer comprising: a semiconductor substrate including a plurality of dies, each die including an active area on a frontside of the substrate; backside metal contacting each die on a backside of the substrate, the backside of the substrate directly opposite the frontside of the substrate; and a gas phase deposited packaging material directly contacting and encapsulating the active area of each die, directly contacting the backside metal of each die, and providing sawing trenches between the dies, wherein the packaging material is an amorphous inorganic or ceramic carbon.

16. The semiconductor wafer of claim 15 , wherein the substrate comprises a thinned substrate.

17. The integrated circuit of claim 1 , further comprising: a leadframe coupled to the backside metal, wherein the packaging material directly contacts the leadframe.

18. The integrated circuit of claim 11 , further comprising: a leadframe coupled to the backside metal, wherein the packaging material directly contacts the leadframe.