An array of non-volatile memory cells arranged in logical columns and logical rows, and associated circuitry to enable reading or writing one or more memory cells on a row in parallel. In some embodiments, the array of memory cells may include a phase change material. In some embodiments, the circuitry may include a write driver, a read driver, a sense amplifier, and circuitry to isolate the memory cells from the sense amplifier with extended refresh.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for accessing a plurality of non-volatile memory elements arranged in a two-dimensional array having a plurality of columns and at least one row, comprising: selecting a plurality of successively larger complements of memory elements during a first series of successive access operations; and selecting a plurality of successively smaller complements of memory elements during a second series of successive access operations.
2. The method of claim 1 , wherein the non-volatile memory elements comprise a phase change material.
3. The method of claim 1 , wherein the step of selecting a plurality of successively larger complements of memory elements comprises selecting memory elements within a row.
4. The method of claim 1 , wherein said selecting a plurality of successively larger complements of memory elements during said first series of successive access operations includes selecting a first number of bits in a first access operation and selecting twice said first number of bits in a second access operation.
5. The method of claim 4 , wherein said selecting a plurality of successively smaller complements of memory elements during said second series of successive access operations includes selecting a second number of bits in a first access operation and selecting half said second number of bits in a second access operation.
6. The method of claim 1 , wherein said first series of successive access operations comprises a plurality of write operations.
7. The method of claim 6 , wherein said second series of successive access operations comprises a plurality of write operations.
8. The method of claim 7 , wherein said selecting successively larger and smaller complements of memory elements written reduces the rate of change of write current over time.
9. A method for reading data from an array of memory elements arranged in columns and rows, comprising: selecting a row of memory elements; and continuously selecting a plurality of memory elements within said selected row, said continuous selection includes selecting a first number of memory elements at a first time and a second number of memory elements at a second time, said first number differing from said second number, said continuous selection being uninterrupted by a refresh cycle.
10. The method of claim 9 , wherein said second number is twice said first number.
11. The method of claim 9 , wherein said selected plurality of memory elements include a phase-change memory element.
12. The method of claim 11 , wherein each of said selected plurality of memory elements is a phase-change memory element.
13. The method of claim 9 , further comprising: connecting a plurality of memory elements in said row to a plurality of sense amplifiers; driving a current through said plurality of memory elements in said row; and measuring the data values stored in said plurality of memory elements with said plurality of sense amplifiers.
14. The method of claim 13 , further comprising: disconnecting at least one memory element of said plurality of memory elements in said row from said plurality of sense amplifiers when the voltage appearing at said at least one memory element exceeds a predetermined voltage.
15. A method for accessing a memory, comprising: applying a memory address to an array of phase-change memory elements, said address having a first portion and a second portion; and while holding said first portion of said memory address constant and without interruption by a refresh cycle: accessing said memory a first time; varying said second portion of said memory address; and accessing said memory a second time.
16. The method of claim 15 , wherein said access at said first time comprises a read operation.
17. The method of claim 16 , wherein said access at said first time further comprises a write operation.
18. The method of claim 16 , wherein said access at said second time comprises a read operation.
19. The method of claim 15 , wherein said array of phase change memory cells comprises: a plurality of phase change memory elements arranged in a plurality of columns and a plurality of rows; a plurality of column lines, wherein each column line connects said memory elements disposed in a particular column; and a plurality of column ground lines disposed in parallel with said column lines; wherein said column ground lines conduct currents from said memory elements addressed by said memory address.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 7, 2010
July 19, 2011
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