A method of manufacturing an active matrix substrate that enables increased productivity due to a reduction in the number of patterning processes and low generation of particles during the patterning processes. The method includes forming a patterned electrode on a substrate, and covering the first electrode with an insulating film. A mono-crystalline semiconductor layer is then formed on the insulating film by attaching a first layer formed on a surface of a semiconductor wafer to the insulating film, and peeling off a portion of the semiconductor wafer. The semiconductor layer is then patterned and doped, in part, by utilizing the patterned electrode as a photo mask for light illuminated from a lower side of the substrate. This results in part in mono-crystalline active layers for thin film transistors, which are then configured to form a pixel for an active matrix substrate.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of manufacturing an active matrix substrate, the method comprising: forming a first electrode having a first pattern on a substrate; forming a first insulating film to cover the first electrode on the substrate; attaching a first layer on a surface of a semiconductor wafer to the first insulating film; transferring the first layer onto the first insulating film to form a semiconductor layer on the first insulating film by electrolysis method; patterning the semiconductor layer to form a first active layer having a first region and a second active layer having a second region, wherein the first region and the second region are doped with different types of dopants from each other; forming a second insulating film to cover the first and second active layers on the first insulating film; and forming a second electrode to couple the first region to the second region on the second insulating film.
2. The method of claim 1 , wherein the patterning of the semiconductor layer to form the first and second active layers comprises: forming a first resist layer on the semiconductor layer to cover a first portion of the semiconductor layer and to expose the first region of the semiconductor layer through an opening in the first resist layer; doping the first region of the semiconductor layer with a dopant through the opening in the first resist layer; removing the first resist layer; forming a second resist layer on the semiconductor layer to cover a second portion of the semiconductor layer and to expose the second region of the semiconductor layer; removing the second resist layer; and patterning the semiconductor layer into a second pattern to form the first active layer having the first region and the second active layer having the second region.
3. The method of claim 2 , wherein a pattern of the opening in the first resist layer is substantially the same as a pattern in which portions other than portions of the first resist layer corresponding to the first pattern of the first electrode are etched.
4. The method of claim 3 , wherein the forming of the first resist layer comprises: exposing the first resist layer to light from a lower side of the substrate in accordance with the first pattern of the first electrode; and etching the first resist layer so as to maintain portions of the first resist layer substantially to correspond in position to the first pattern of the first electrode.
5. The method of claim 2 , wherein the patterning of the semiconductor layer into the second pattern is performed prior to the forming of the first resist layer.
6. The method of claim 1 , wherein the attaching of the first layer on the surface of the semiconductor wafer to the first insulating film comprises: forming the first layer on the surface of the semiconductor wafer; heating the semiconductor wafer with a first temperature and the first insulating film with a second temperature different from the first temperature; bringing the first layer on the surface of the semiconductor wafer into contact with the first insulating film; applying a voltage between the semiconductor wafer and the first insulating film; and peeling a portion of the semiconductor wafer from the first insulating film such that the first layer remains attached to the first insulating film.
7. The method of claim 6 , wherein the forming of the first layer on the surface of the semiconductor wafer comprises ion implanting a gas comprising hydrogen ions into the surface of the semiconductor wafer.
8. The method of claim 1 , wherein the semiconductor wafer comprises mono-crystalline silicon.
9. A method of manufacturing an organic light emitting display device, the method comprising: forming a first gate electrode, a second gate electrode, and a third gate electrode on a substrate; forming a first insulating film to cover the first gate electrode on the substrate; attaching a first layer on a surface of a semiconductor wafer to the first insulating film; transferring the first layer onto the first insulating film to form a semiconductor layer on the first insulating film by electrolysis method; patterning the semiconductor layer to form a first active layer having a first region, a second active layer having a second region, and a third active layer having a third region, wherein at least the first region and the second region are doped with different types of dopants from each other; forming a second insulating film to cover the first through third active layers on the first insulating film; forming a second electrode to couple the first region to the second region and forming a pixel electrode coupled to the third region on the second insulating film; forming a third insulating film to cover the second electrode and the pixel electrode on the second insulating film; forming an opening in the third insulating film to expose at least one portion of the pixel electrode; forming an organic film comprising a light emitting layer on the at least one portion of the pixel electrode exposed through the opening in the third insulating film; and forming a facing electrode to cover the organic film.
10. The method of claim 9 , wherein the forming of the first through third active layers comprises: forming a first resist layer on the semiconductor layer to cover the semiconductor layer and having an opening to expose the first region of the semiconductor layer; doping the first region of the semiconductor layer with a dopant through the opening of the first resist layer; removing the first resist layer; forming a second resist layer on the semiconductor layer to cover the semiconductor layer and having an opening to expose the second and third regions of the semiconductor layer; doping the second and third regions of the semiconductor layer with a dopant through the opening of the second resist layer; and removing the second resist layer.
11. The method of claim 10 , wherein a pattern of the opening in the first resist layer is substantially the same as a pattern in which portions other than portions of the first resist layer corresponding to the first gate electrode, the second gate electrode, and the third gate electrode are etched.
12. The method of claim 11 , wherein the forming of the first resist layer comprises: exposing the first resist layer to light from a lower side of the substrate in accordance with a pattern of the first gate electrode, the second gate electrode, and the third gate electrode; and etching the first resist layer so as to maintain portions of the first resist layer to substantially correspond in position to the pattern of the first through third gate electrodes.
13. The method of claim 10 , wherein the patterning of the semiconductor layer is performed prior to the forming of the first resist layer.
14. The method of claim 10 , wherein the attaching of the first layer on the surface of the semiconductor wafer to the first insulating film comprises: forming the first layer on the surface of the semiconductor wafer; heating the semiconductor wafer with a first temperature and the first insulating film with a second temperature different from the first temperature; bringing the first layer on the surface of the semiconductor wafer into contact with the first insulating film; applying a voltage between the semiconductor wafer and the first insulating film; and peeling a portion of the semiconductor wafer from the first insulating film such that the first layer remains attached to the first insulating film.
15. The method of claim 9 , wherein forming the first layer on the surface of the semiconductor wafer comprises ion implanting a gas comprising hydrogen ions into a surface of the semiconductor wafer.
16. The method of claim 9 , wherein the semiconductor wafer is formed of mono-crystalline silicon.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 27, 2010
July 26, 2011
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