An input/output (IO) interface includes a data encoder which encodes each of a plurality of pieces of parallel data having different timings and generates a plurality of pieces of encoded data, and an alternating current (AC) coupling transmission unit which transmits the plurality of encoded data in an AC coupling method. The data encoder compares first parallel data with second parallel data from among the plurality of pieces of parallel data on a bit-by-bit basis and obtains the number of bits whose logic states have transited between the first parallel data and the second parallel data. When the number of bits whose logic states have transited is greater than or equal to a reference number of bits, the data encoder inverts bit values of the second parallel data to generate the encoded data. When the number of bits whose logic states have transited is less than the reference number of bits, the data encoder maintains the bit values of the second parallel data to generate the encoded data.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An input/output (IO) interface comprising: a data encoder encoding each of a plurality of pieces of parallel data having different timings and generating a plurality of pieces of encoded data; and an alternating current (AC) coupling transmission unit transmitting the plurality of pieces of encoded data by performing an AC coupling method, wherein: the data encoder compares first parallel data with second parallel data from among the plurality of pieces of parallel data on a bit-by-bit basis and obtains a number of bits whose logic states have transited between the first parallel data and the second parallel data; when the number of bits whose logic states have transited is greater than or equal to a reference number of bits, the data encoder inverts bit values of the second parallel data to generate the encoded data, and when the number of bits whose logic states have transited is less than the reference number of bits, the data encoder maintains the bit values of the second parallel data to generate the encoded data; the data encoder generates encoding flags; when the encoded data is generated by maintaining the bit values of the second parallel data, the data encoder sets the encoding flags to have a first logic state; and when the encoded data is generated by inverting the bit values of the second parallel data, the data encoder sets the encoding flags to have a second logic state.
2. The IO interface of claim 1 , wherein: the AC coupling transmission unit transmits the plurality of pieces of encoded data via a channel; and the AC coupling transmission unit is connected to the channel via a capacitor.
3. The IO interface of claim 1 , wherein the AC coupling transmission unit comprises: a data transmitter; and a capacitor serially connected to the data transmitter.
4. The IO interface of claim 1 , wherein the IO interface is an IO interface of a semiconductor memory.
5. An IO interface comprising: a data encoder encoding at least one piece of parallel data and generating at least one piece of first encoded data; a logic state transition controller transforming the at least one piece of first encoded data into second encoded data; and an AC coupling transmission unit transmitting the second encoded data in an AC coupling method, wherein: the data encoder detects logic states of bits of the at least one piece of parallel data; when the number of bits having a first logic state is greater than or equal to a reference number of bits, the data encoder inverts the logic states of the bits of the at least one piece of parallel data to generate the first encoded data, and when the number of bits having the first logic state is less than the reference number of bits, the data encoder maintains the logic states of the bits of the at least one piece of parallel data to generate the second encoded data; and when bits having the first logic state from among the bits included in the at least one piece of first encoded data are detected, the logic state transition controller controls a logic state transition to occur in corresponding bits from among the bits included in the second encoded data; the data encoder generates encoding flags; when the at least one piece of first encoded data is generated by maintaining the logic states of the bits of the at least one piece of parallel data, the data encoder sets the encoding flags to have the first logic state; and when the at least one piece of first encoded data is generated by inverting the logic states of the bits of the at least one piece of parallel data, the data encoder sets the encoding flags to have a second logic state.
6. The IO interface of claim 5 , wherein the first logic state is logic low.
7. The IO interface of claim 5 , wherein the logic state transition controller comprises: an inverter sequentially receiving and inverting the bits included in the second encoded data; a multiplexer selecting and outputting one of a bit inverted by the inverter and a non-inverted bit in response to a logic state of the at least one piece of first encoded data; and a flip-flop outputting the second encoded data in response to an output of the multiplexer.
8. The IO interface of claim 5 , wherein: the AC coupling transmission unit transmits the second encoded data via a channel; and the AC coupling transmission unit is connected to the channel via a capacitor.
9. The IO interface of claim 5 , wherein the AC coupling transmission unit comprises: a data transmitter; and a capacitor serially connected to the data transmitter.
10. An IO data transmitting method comprising: encoding each of a plurality of pieces of parallel data having different timings and generating a plurality of pieces of encoded data; and transmitting the plurality of pieces of encoded data by performing an AC coupling method, wherein: in the encoding of the plurality of pieces of parallel data, first parallel data is compared with second parallel data from among the plurality of pieces of parallel data on a bit-by-bit basis, and a number of bits whose logic states have transited between the first parallel data and the second parallel data is obtained; when the number of bits whose logic states have transited is greater than or equal to a reference number of bits, bit values of the second parallel data are inverted to generate the encoded data, and when the number of bits whose logic states have transited is less than the reference number of bits, the bit values of the second parallel data are maintained to generate the encoded data; generating encoding flags; when the encoded data is generated by maintaining the bit values of the second parallel data, setting the encoding flags to have a first logic state; and when the encoded data is generated by inverting the bit values of the second parallel data, setting the encoding flags to have a second logic state.
11. The IO data transmitting method of claim 10 , further comprising: receiving the encoded data transmitted in the transmitting of the encoded data in the AC coupling method; and decoding the received encoded data.
12. An IO data transmitting method comprising: encoding at least one piece of parallel data and generating at least one piece of first encoded data; transforming the at least one piece of first encoded data into second encoded data; and transmitting the second encoded data by performing an AC coupling method, wherein: in the encoding of the at least one piece of parallel data, logic states of bits of the at least one piece of parallel data are detected; when the number of bits having a first logic state is greater than or equal to a reference number of bits, the logic states of the bits of the at least one piece of parallel data are inverted to generate the first encoded data, and when the number of bits having the first logic state is less than the reference number of bits, the logic states of the bits of the at least one piece of parallel data are maintained to generate the second encoded data; in the transforming of the first encoded data into the second encoded data, when bits having the first logic state from among the bits included in the first encoded data are detected, a logic state transition is controlled to occur in corresponding bits from among the bits included in the second encoded data; generating encoding flags; when the at least one piece of first encoded data is generated by maintaining the logic states of the bits of the at least one piece of parallel data, setting the encoding flags to have the first logic state; and when the at least one piece of first encoded data is generated by inverting the logic states of the bits of the at least one piece of parallel data, setting the encoding flags to have a second logic state.
13. The IO data transmitting method of claim 12 , further comprising: receiving the second encoded data transmitted in the transmitting of the second encoded data by performing the AC coupling method; and decoding the received second encoded data.
14. An IO interface comprising: a data encoder encoding each of a plurality of pieces of parallel data having different timings and generating a plurality of pieces of encoded data having different timings; and an AC coupling transmission unit transmitting the plurality of pieces of encoded data by performing an AC coupling method, wherein: the data encoder encodes the plurality of pieces of parallel data so that the number of bits whose logic states transit between first encoded data and second encoded data is minimized; the data encoder compares first parallel data with second parallel data from among the plurality of pieces of parallel data on a bit-by-bit basis and obtains a number of bits whose logic states have transited between the first parallel data and the second parallel data; when the number of bits whose logic states have transited is greater than or equal to a reference number of bits, the data encoder inverts bit values of the second parallel data to generate the encoded data, and when the number of bits whose logic states have transited is less than the reference number of bits, the data encoder maintains the bit values of the second parallel data to generate the encoded data; the data encoder generates encoding flags; when the encoded data is generated by maintaining the bit values of the second parallel data, the data encoder sets the encoding flags to have a first logic state; and when the encoded data is generated by inverting the bit values of the second parallel data, the data encoder sets the encoding flags to have a second logic state.
15. The IO interface of claim 14 , further comprising: an AC coupling reception unit receiving the plurality of pieces of encoded data from another IO interface; and a data decoder decoding the plurality of pieces of received encoded data.
16. The IO interface of claim 14 , wherein: the AC coupling transmission unit transmits the plurality of encoded data via a channel; and the AC coupling transmission unit is connected to the channel via a capacitor.
17. An IO interface comprising: a data encoder encoding at least one piece of parallel data and generating at least one piece of first encoded data; a logic state transition controller transforming the first encoded data into second encoded data; and an AC coupling transmission unit transmitting the second encoded data by performing an AC coupling method, wherein: the data encoder detects logic states of bits of the parallel data and encodes the at least one piece of parallel data so that the number of bits having a first logic state is minimized, thereby generating the first encoded data; when bits having the first logic state from among the bits included in the first encoded data are detected, the logic state transition controller controls logic state transition to occur in corresponding bits from among the bits included in the second encoded data; when the number of bits having a first logic state is greater than or equal to a reference number of bits, the data encoder inverts the logic states of the bits of the parallel data to generate the first encoded data; when the number of bits having the first logic state is less than the reference number of bits, the data encoder maintains the logic states of the bits of the parallel data to generate the second encoded data; the data encoder generates encoding flags; when the at least one piece of first encoded data is generated by maintaining the logic states of the bits of the at least one piece of parallel data, the data encoder sets the encoding flags to have the first logic state; and when the at least one piece of first encoded data is generated by inverting the logic states of the bits of the at least one piece of parallel data, the data encoder sets the encoding flags to have a second logic state.
18. The IO interface of claim 17 , further comprising: an AC coupling reception unit receiving the second encoded data from another IO interface; and a data decoder decoding the received second encoded data.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 25, 2009
July 26, 2011
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.