The semiconductor device includes first and second common source semiconductor layers respectively extending in a first direction, first and second logic gate circuits respectively composed of at least one three-dimensional P-type FET and a three-dimensional N-type FET. The sources of the three-dimensional P-type FETs in the first and second logic gate circuits are joined to the first common source semiconductor layer. The sources of the three-dimensional N-type FETs in the first and second logic gate circuits are joined to the second common source semiconductor layer. The semiconductor layers of the three-dimensional P-type and N-type FETs in the first logic gate circuit are joined in their drain side, and The semiconductor layers of the three-dimensional P-type and N-type FETs in the second logic gate circuit are joined in their drain side. The dissipation of the FinFET can be improved.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: a first common source semiconductor layer configured to extend in a first direction; a second common source semiconductor layer configured to extend in the first direction; a first logic gate circuit composed of at least one three-dimensional P-type FET and a three-dimensional N-type FET; and a second logic gate circuit composed of at least one three-dimensional P-type FET and a three-dimensional N-type FET, wherein a source of the three-dimensional P-type FET in the first logic gate circuit and a source of the three-dimensional P-type FET in the second logic gate circuit are joined to the first common source semiconductor layer, a source of the three-dimensional N-type FET in the first logic gate circuit and a source of the three-dimensional N-type FET in the second logic gate circuit are joined to the second common source semiconductor layer, a drain of the three-dimensional P-type FET of the first logic gate circuit and a drain of the three-dimensional N-type FET of the first logic gate circuit are joined to each other, and a drain of the three-dimensional P-type FET of the second logic gate circuit and a drain of the three-dimensional N-type FET of the second logic gate circuit are joined to each other.
2. The semiconductor device according to claim 1 , wherein each of the three-dimensional P-type FET and the three-dimensional N-type FET is a FinFET or a double gate FET.
3. The semiconductor device according to claim 1 , wherein a direction of a signal transmitted from the first logic gate circuit to the second logic gate circuit is the first direction.
4. The semiconductor device according to claim 1 , wherein a channel region of the three-dimensional P-type FET and a channel region of a semiconductor layer of the three-dimensional N-type FET which are included in the first logic gate circuit are aligned along a second direction perpendicular to the first direction, and a channel region of a semiconductor layer of the three-dimensional P-type FET and a channel region of a semiconductor layer of the three-dimensional N-type FET which are included in the second logic gate circuit are aligned along the second direction.
5. The semiconductor device according to claim 1 , wherein a channel region of a semiconductor layer of the three-dimensional P-type FET and a channel region of a semiconductor layer of the three-dimensional N-type FET which are included in the first logic gate circuit are aligned along the first direction, a part of a source region of the three-dimensional P-type FET and a part of a source region of the three dimensional N-type FET which are included in the first logic gate circuit are arranged in a second direction perpendicular to the first direction against the channel region of the first logic gate circuit, and a part of a source region of the three-dimensional P-type FET and a part of a source region of the three dimensional N-type FET which are included in the second logic gate circuit are arranged in a second direction perpendicular to the first direction against the channel region of the second logic gate circuit.
6. The semiconductor device according to claim 1 , wherein a drain region of the three-dimensional P-type FET and a drain region of the three-dimensional N-type FET which are included in the first logic gate circuit are joined to form a p-n junction.
7. The semiconductor device according to claim 6 , wherein a drain electrode contact is formed to connect to a position where a drain region of the three-dimensional P-type FET and a drain region of the three-dimensional N-type FET which are included in the first logic gate circuit are joined to form a p-n junction.
8. The semiconductor device according to claim 1 , wherein a drain region of the three-dimensional P-type FET and a drain region of the three-dimensional N-type FET which are included in the first logic gate circuit are joined via an intrinsic region to which impurity is not doped.
9. The semiconductor device according to claim 1 , wherein at least a part of a region composed of a source and a drain of the three-dimensional P-type FET and the three-dimensional N-type FET has a metal silicide structure.
10. The semiconductor device according to claim 1 , the first common source semiconductor layer, the second common source semiconductor layer, the three-dimensional P-type FET and the three-dimensional N-type FET which are included in the first logic gate circuit, and the three-dimensional P-type FET and the three-dimensional N-type FET which are included in the second logic gate circuit are arranged to form a quadrangular or more polygonal loop.
11. The semiconductor device according to claim 1 , wherein the first logic gate circuit and the second logic gate circuit are respectively one of an inverter circuit, NAND circuit, NOR circuit and a clocked inverter circuit.
12. The semiconductor device according to claim 1 , wherein a width of the first common source semiconductor layer and a width of the second common source semiconductor layer are larger than the three-dimensional P-type FET and the three-dimensional N-type FET.
13. The semiconductor device according to claim 1 , wherein a sum of a pattern area of the first common source semiconductor layer and a pattern area of the second common source semiconductor layer is larger than a sum of a semiconductor layer of the three-dimensional P-type FET and a semiconductor layer of the three-dimensional N-type FET.
14. The semiconductor device according to claim 1 , wherein the first common source semiconductor layer is connected to an interconnection having a power supply potential, and the second common source semiconductor layer is connected to an interconnection having a ground potential.
15. The semiconductor device according to claim 14 , wherein the first common source semiconductor layer and the interconnection having the power supply potential are connected through a plurality of contacts, and the second common source semiconductor layer and the interconnection having the ground potential are connected through a plurality of contacts.
16. A semiconductor device comprising: an insulating layer; a first semiconductor block formed on said insulating layer extending in a first direction; a second semiconductor block in contact with said first semiconductor block; a third semiconductor block in contact with said first semiconductor block; a first gate electrode formed adjacent to a side surface of said second semiconductor block; and a second gate electrode formed adjacent to a side surface of said third semiconductor block, wherein each of said first semiconductor block, said second semiconductor block, and said third semiconductor block has a same height from a top surface of said insulating layer.
17. The semiconductor device according to claim 16 , wherein said second semiconductor block has first source node at one end thereof connected to said first semiconductor block and first drain node at another end thereof, and wherein said third semiconductor block has second source node at one end thereof connected to said first semiconductor block and second drain node at another end thereof, and wherein said first and said second source nodes are supplied with first power potential through the first semiconductor block and said first and said second drain nodes output signals in response to respective potentials at said first and said second gates.
18. The semiconductor device according to claim 17 , further comprising: a fourth semiconductor block formed on said insulating layer extending in the first direction; a fifth semiconductor block in contact with said fourth semiconductor block; a third gate electrode formed on a side surface of said fifth semiconductor block, said fifth semiconductor block has third source node at one end thereof connected to said fourth semiconductor block and third drain node at another end thereof, said third source node is supplied with second power potential through the fourth semiconductor block and said third drain node outputs signal in response to potential at said third gate, said first drain node and third drain node are in contact with each other.
19. The semiconductor device according to claim 18 , further comprising: a sixth semiconductor block in contact with said fourth semiconductor block; a fourth gate electrode formed on a side surface of said sixth semiconductor block, said sixth semiconductor block has fourth source node at one end thereof connected to said fourth semiconductor block and fourth drain node at another end thereof, said second drain node and fourth drain node are in contact with each other.
20. The semiconductor device according to claim 18 , further comprising: a sixth semiconductor block in contact with said fourth semiconductor block; and a fifth gate electrode formed on a side surface of said sixth semiconductor block, said fifth gate electrode arranged between said third drain node and said third gate electrode.
21. A semiconductor device comprising: an insulating layer; a first semiconductor block formed on said insulating layer extending in a first direction; a second semiconductor block in contact with said first semiconductor block; a third semiconductor block in contact with said first semiconductor block; a first gate electrode formed adjacent to a side surface of said second semiconductor block; and a second gate electrode formed adjacent to a side surface of said third semiconductor block, wherein each of said first semiconductor block, said second semiconductor block, and said third semiconductor block has a same height from a top surface of said insulating layer, and wherein each of the first gate electrode and the second gate electrode has a bent portion, wherein the bent portion is bent in a length direction of a channel.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 27, 2008
August 2, 2011
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.