An electronic device includes a transistor, wherein the electronic device can include a semiconductor layer having a primary surface, a channel region, a gate electrode, a source region, a conductive electrode, and an insulating layer lying between the primary surface of the semiconductor layer and the conductive electrode. The insulating layer has a first region and a second region, wherein the first region is thinner than the second region. The channel region, gate electrode, source region, or any combination thereof can lie closer to the first region than the second region. The thinner portion can allow for faster switch of the transistor, and the thicker portion can allow a relatively large voltage difference to be placed across the insulating layer. Alternative shapes for the transitions between the different regions of the insulating layer and exemplary methods to achieve such shapes are also described.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An electronic device comprising: a semiconductor layer having a primary surface and a trench therein extending from the primary surface; a channel region; a conductive electrode overlying, spaced apart, and electrically insulated from all conductive material that lies within the trench; and an insulating layer lying between the primary surface and the conductive electrode, wherein the insulating layer has a first region and a second region, the first region is thinner than the second region, and the channel region lies closer to the first region than the second region.
2. The electronic device of claim 1 , wherein the second region comprises at least one more film as compared to the first region.
3. The electronic device of claim 1 , further comprising: a source region lying adjacent to the channel region; a conductive structure lying within the trench in the semiconductor layer; and a surface doped region lying between the channel region and the conductive structure, wherein: the first region of the insulating layer overlies the surface doped region; and the second region of the insulating layer overlies the conductive structure.
4. The electronic device of claim 3 , further comprising a drain and is designed to normally operate at a source-to-drain voltage difference of at least approximately 20 volts.
5. The electronic device of claim 3 , wherein; the conductive electrode has a first region and a second region; and a bottom surface of the first region of the conductive electrode lies at a first elevation, and a bottom surface of the second region of the conductive electrode lies at a second elevation that is different from the first elevation.
6. The electronic device of claim 3 , wherein the surface doped region extends approximately 0.2 micron to approximately 3.0 microns along the primary surface of the semiconductor layer from the conductive structure toward the source region.
7. An electronic device comprising: a semiconductor layer having a primary surface and a trench therein extending from the primary surface; a conductive structure within the trench; an insulating layer including a first region and a second region, wherein the second region is thicker than the first region, and the second region overlies the conductive structure; and a conductive electrode overlying the first and second regions of the insulating layer and the conductive structure, wherein: the conductive electrode has a first region and a second region; a bottom surface of the first region of the conductive electrode overlies the first region of the insulating layer and lies at a first elevation, and a bottom surface of the second region of the conductive electrode overlies the second region of the insulating layer and lies at a second elevation that is different from the first elevation.
8. The electronic device of claim 7 , further comprising: a gate electrode overlying the semiconductor layer; and a gate signal line overlying the primary surface of the semiconductor layer and the conductive electrode, wherein: the gate electrode does not overlie the conductive electrode; and the conductive electrode is configured to be at a substantially constant voltage when the electronic device is in a normal operating state.
9. The electronic device of claim 8 , wherein: a portion of the conductive electrode lies adjacent to the gate electrode and has a first surface and a second surface opposite the first surface; the primary surface is closer to the first surface than the second surface; and within an area occupied by a transistor, including the gate electrode, each of the first and second surfaces of the conductive electrode lies at elevations between lowermost and uppermost points of the gate electrode.
10. The electronic device of claim 7 , further comprising: a gate electrode overlying the semiconductor layer; a source region lying adjacent to the gate electrode; a channel region lying adjacent to the source region and the gate electrode; a conductive structure lying within a trench in the semiconductor layer; an underlying doped region that underlies the semiconductor layer and the conductive structure; and a surface doped region spaced apart from the underlying doped region, wherein: the channel region lies closer to the surface doped region as compared to the conductive structure; the first region of the insulating layer overlies the surface doped region; and the second region of the insulating layer overlies the conductive structure.
11. The electronic device of claim 10 , further comprising a drain, wherein: the electronic device comprises a transistor that comprises the source, gate electrode, and drain; and the transistor is designed to normally operate at a source-to-drain voltage difference of at least approximately 20 volts.
12. The electronic device of claim 10 , wherein: the electronic device comprises a transistor that comprises the source and gate electrode; and the transistor is designed to normally operate at a source-to-conductive structure voltage difference of at least approximately 20 volts.
13. The electronic device of claim 10 , wherein the surface doped region extends approximately 0.2 micron to approximately 3.0 microns along the primary surface from the conductive structure toward the source region.
14. A process of forming an electronic device comprising: providing a workpiece comprising a substrate, including an underlying doped region, and a semiconductor layer overlying the underlying doped region, wherein the semiconductor layer has a primary surface spaced apart from the underlying doped region; forming an insulating layer over the semiconductor layer, wherein the insulating layer has a first region and a second region, and the first region is thinner than the second region; forming a conductive electrode over the first and second regions of the insulating layer, wherein the conductive electrode is formed after forming the insulating layer having the first region thinner than the second region; and forming a source region that lies closer to the first region of the insulating layer compared to the second region of the insulating layer.
15. The process of claim 14 , wherein forming the insulating layer comprises: depositing the insulating layer; forming a mask that defines an opening overlying the first region of the insulating layer; and isotropically etching the insulating layer within the first region.
16. The process of claim 14 , wherein forming the insulating layer comprises: depositing an insulating layer; patterning the insulating layer to define an opening overlying the first region of the insulating layer; and forming an insulating sidewall spacer within the opening.
17. The process of claim 14 , wherein forming the insulating layer comprises: depositing the insulating layer; forming a mask that defines an opening overlying the first region of the insulating layer; and simultaneously etching exposed portions of the insulating layer and the mask during at least one point time, such that from a cross-sectional view, the insulating layer has a substantially linear slope after simultaneously etching.
18. The process of claim 14 , wherein forming the insulating layer comprises: depositing the insulating layer; forming a mask that defines an opening overlying the first region of the insulating layer; anisotropically etching the insulating layer underlying the opening to etch through a part of a thickness of the insulating layer; isotropically etching a portion of the mask to widen the opening in the mask after anisotropically etching the insulating layer; and anisotropically etching the insulating layer underlying the widened opening after isotropically etching the portion of the mask.
19. The process of claim 14 , further comprising: forming a trench within the semiconductor layer, wherein the trench extends from the primary surface toward the underlying doped region; forming a conductive structure lying within the trench; and forming a surface doped region spaced apart from the underlying doped region, wherein: the first region of the insulating layer overlies the surface doped region; and the second region of the insulating layer overlies the conductive structure.
20. The process of claim 19 , wherein the electronic device includes a transistor that includes the source region, wherein the transistor is designed to normally operate at a source-to-conductive structure voltage difference of at least approximately 20 volts.
21. The process of claim 20 , wherein the surface doped region extends approximately 0.2 micron to approximately 3.0 microns along the primary surface from the conductive structure toward the source region.
22. The process of claim 19 , further comprising: forming a gate signal line over the conductive electrode; and forming a gate electrode over the primary surface of the semiconductor layer; wherein: the gate electrode does not overlie the conductive electrode; the conductive electrode lies between the gate signal line and each of the conductive structure and the surface doped region; and in a finished form of the electronic device, the conductive electrode is configured to be at a substantially constant voltage when the electronic device is in a normal operating state.
23. The process of claim 22 , wherein the transistor is designed to normally operate at a source-to-drain voltage difference of at least approximately 20 volts.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 17, 2008
August 2, 2011
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