A system and method for issuing load-dependent instructions in an issue queue in a processing unit. A load miss queue is provided. The load miss queue comprises a physical address field, an issue queue position field, a valid identifier field, a source identifier field, and a data type field. A load instruction that misses a first level cache is dispatched, and both the physical address field and the data type field are set. A load-dependent instruction is identified. In response to identifying the load-dependent instruction, each of the issue queue position field, valid identifier field, and source identifier field are set. If the issue queue position field refers to a flushed instruction, the valid identifier field is cleared. The load instruction is recycled, and a value of the valid identifier field is determined. The load-dependent instruction is then selected for issue on a next processing cycle independent of an age of the load-dependent instruction.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A computer-implementable method for issuing load-dependent instructions from an issue queue in a processing unit in a data processing system, said computer-implementable method comprising: providing a load miss queue comprising a physical address field that indicates where load instruction data is stored for said load miss queue, an issue queue position field that indicates an issue queue position of a load-dependent instruction, a valid identifier field that indicates if said load-dependent instruction is valid, a source identifier field that indicates a source of said load-dependent instruction that is dependent on a load instruction, and a data type field that indicates a type of said load instruction data; dispatching said load instruction that misses a first level cache; in response to dispatching said load instruction, setting both of said physical address field and said data type field; identifying said load-dependent instruction, wherein said load-dependent instruction comprises one or more from the group consisting of: an instruction present in one of a plurality of issue queues; and an instruction dispatched from one of a plurality of latches; in response to identifying said load-dependent instruction, setting each of said issue queue position field, said valid identifier field, and said source identifier field; determining if said issue queue position field refers to a flushed instruction; in response to determining said issue queue position field refers to a flushed instruction, clearing said valid identifier field, wherein clearing said valid identifier field further comprises: comparing said issue queue position field against flushed instructions referred to by other issue queue position fields within said load miss queue; in response to comparing said issue queue position field against flushed instructions referred to by other issue queue position fields, clearing said valid identifier field; recycling said load instruction, in response to recycling said load instruction, determining a value of said valid identifier field; and in response to determining said value of said valid identifier field, selecting said load-dependent instruction for issue on a next processing cycle independent of an age of said load-dependent instruction.
2. The computer-implementable method according to claim 1 , wherein clearing said valid identifier field further comprises: clearing all valid identifier fields within said load miss queue that correspond to a flushed thread.
3. The computer-implementable method according to claim 1 , wherein setting said valid identifier field further comprises: determining if all sources of said load-dependent instruction are ready; and in response to determining if all sources of said load-dependent instruction are ready, setting said valid identifier field.
4. The computer-implementable method according to claim 1 , further comprising: in response to determining said value of said valid identifier field, selecting said load-dependent instruction for issue based on said age of said load-dependent instruction.
5. A system for issuing load-dependent instructions from an issue queue in a processing unit in a data processing system, said system comprising: at least one processing unit; an interconnect coupled to said at least one processing unit; and a computer usable medium embodying computer program code, said computer usable medium being coupled to said interconnect, said computer program code comprising instructions executable by said at least one processing unit and configured for: providing a load miss queue comprising a physical address field that indicates where load instruction data is stored for said load miss queue, an issue queue position field that indicates an issue queue position of a load-dependent instruction, a valid identifier field that indicates if said load-dependent instruction is valid, a source identifier field that indicates a source of said load-dependent instruction that is dependent on a load instruction, and a data type field that indicates a type of said load instruction data; dispatching said load instruction that misses a first level cache; in response to dispatching said load instruction, setting both of said physical address field and said data type field; identifying said load-dependent instruction, wherein said load-dependent instruction comprises one or more from the group consisting of: an instruction present in one of a plurality of issue queues; and an instruction dispatched from one of a plurality of latches; in response to identifying said load-dependent instruction, setting each of said issue queue position field, said valid identifier field, and said source identifier field; determining if said issue queue position field refers to a flushed instruction; in response to determining said issue queue position field refers to a flushed instruction, clearing said valid identifier field, wherein said instructions are further configured for: comparing said issue queue position field against flushed instructions referred to by other issue queue position fields within said load miss queue; in response to comparing said issue queue position field against flushed instructions referred to by other issue queue position fields, clearing said valid identifier field; recycling said load instruction, in response to recycling said load instruction, determining a value of said valid identifier field; and in response to determining said value of said valid identifier field, selecting said load-dependent instruction for issue on a next processing cycle independent of an age of said load-dependent instruction.
6. The system according to claim 5 , wherein said instructions are further configured for: clearing all valid identifier fields within said load miss queue that correspond to a flushed thread.
7. The system according to claim 5 , wherein said instructions are further configured for: determining if all sources of said load-dependent instruction are ready; and in response to determining if all sources of said load-dependent instruction are ready, setting said valid identifier field.
8. The system according to claim 5 , wherein said instructions are further configured for: in response to determining said value of said valid identifier field, selecting said load-dependent instruction for issue based on said age of said load-dependent instruction.
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September 23, 2008
August 2, 2011
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