To reduce the size and improve the power added efficiency of an RF power module having an amplifier element composed of a silicon power MOSFET, the on resistance and feedback capacitance, which were conventionally in a trade-off relationship, are reduced simultaneously by forming the structure of an offset drain region existing between a gate electrode and an n+ type drain region of the power MOSFET into a double offset one. More specifically, this is accomplished by adjusting the impurity concentration of an n− type offset drain region, which is closest to the gate electrode, to be relatively low and adjusting the impurity concentration of an n type offset drain region, which is distant from the gate electrode, to be relatively high.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device including an MOSFET, comprising: source regions and drain regions formed in a semiconductor substrate of a first conductivity type and being spaced apart, in a first direction, by channel regions of a second conductivity type, the source and the drain regions each having the second conductivity type; semiconductor regions of the second conductivity type formed in the semiconductor substrate and arranged between the source regions adjacent to each other in the first direction; gate electrodes formed over the semiconductor substrate and extending in a second direction crossing the first direction; metal wirings formed over the semiconductor substrate; and a plurality of sinker layers formed in the semiconductor substrate, wherein each of the sinker layers is buried in a trench formed in the semiconductor substrate such that at least one of the semiconductor regions is arranged in a vicinity of a surface the sinker layer, such that the sinker layer is electrically connected to the semiconductor region and to the channel region and such that the sinker layer has a plane pattern having a long side in the second direction and is electrically connected to the metal wiring through a plurality of first contact holes arranged in the second direction.
2. A semiconductor device according to claim 1 , wherein the metal wiring is electrically connected to the source regions through second contact holes spaced apart from the first contact holes.
3. A semiconductor device including a power MOSFET, comprising: a source region and a drain region formed in a semiconductor substrate of a first conductivity type and being spaced apart, in a first direction, by a channel formation region of a second conductive type, the source and the drain region having the second conductive type, a semiconductor region of the second conductive type formed in the semiconductor substrate and arranged adjacent to the source region in the first direction; a gate electrode formed over the semiconductor substrate and extending in a second direction crossing the first direction; a metal wiring formed over the semiconductor substrate; and a sinker layer buried in a trench formed in the semiconductor substrate such that the semiconductor region is arranged in the vicinity of the surface the sinker layer, such that the sinker layer is electrically connected to the semiconductor region and the channel formation region and such that the sinker layer has a plane pattern having a long side in the second direction and are electrically connected to the metal wiring through a plurality of first contact holes arranged in the second direction.
4. A semiconductor device according to claim 3 , wherein the sinker layer is comprised of a metal.
5. A semiconductor device according to claim 3 , wherein the sinker layer is comprised of a silicon film, wherein the sinker layer has the first conductive type such that an impurity concentration of the semiconductor regions is greater than an impurity concentration of the sinker layer.
6. A semiconductor device according to claim 3 , wherein the metal wiring is electrically connected to the source region through a second contact hole spaced apart from the first contact holes.
7. A semiconductor device according to claim 1 , wherein the MOSFET is a power MOSFET.
8. A semiconductor device according to claim 1 , wherein the sinker layer is comprised of a metal film.
9. A semiconductor device according to claim 1 , wherein the sinker layer is comprised of a silicon film, wherein the sinker layer has the first conductivity type such that an impurity concentration of the semiconductor regions is greater than an impurity concentration of the sinker layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 25, 2010
August 9, 2011
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