A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic layer of the junction. A current through a selected word line, coupled to the control gate, generates a first magnetic field. A current through a cell select line generates a second magnetic field that is orthogonal to the first magnetic field. This changes the magnetic orientation of the upper magnetic layer of the junction to lower its resistance, thus allowing a write/erase voltage on a program/erase line to program/erase the floating gate.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for erasing a memory cell comprising a magnetic tunneling junction, the method comprising: generating a first magnetic field in response to a first current through a selected word line coupled to the memory cell; generating a second magnetic field in response to a second current through a cell select line located over the memory cell and orthogonal to the selected word line, and biasing a program/erase line with an erase voltage.
2. The method of claim 1 wherein the erase voltage is substantially equal to OV.
3. The method of claim 1 wherein the erase voltage is a positive voltage.
4. The method of claim 1 wherein the memory cell comprises a floating gate around a control gate.
5. The method of claim 4 wherein the erase voltage is configured to attract electrons from the floating gate.
6. The method of claim 4 wherein the control gate comprises a second polysilicon layer over an oxide-nitride-oxide layer and a polycide layer over the second polysilicon layer.
7. The method of claim 4 wherein an insulator layer separates the floating gate from the control gate.
8. The method of claim 1 wherein an electrode is formed over the magnetic tunneling junction.
9. The method of claim 1 wherein the magnetic tunneling junction comprises a first magnetic layer over a pinning layer, a tunneling barrier over the first magnetic layer, and a second magnetic layer over the tunneling barrier.
10. The method of claim 9 wherein a tunnel dielectric separates the first magnetic layer and the second magnetic layer.
11. The method of claim 10 wherein the tunnel dielectric layer comprises an oxide material.
12. The method of claim 9 wherein the first magnetic layer is a fixed magnetic layer and the second magnetic layer is a free magnetic layer.
13. The method of claim 1 wherein the erase voltage is configured to reduce a resistance of the magnetic tunneling junction.
14. The method of claim 13 wherein the erase voltage reduces the resistance by the first and second magnetic fields.
15. The method of claim 1 wherein the memory cell is configured to operate as one of either a multiple level cell or a single level cell.
16. The method of claim 15 and further comprising opening the magnetic tunneling junction for a predetermined time period to program a threshold voltage.
17. The method of claim 16 wherein a charge is transferred from the program/erase line over the magnetic tunneling junction.
18. The method of claim 16 wherein a level of charge transferred to a floating gate changes in response to the predetermined time period.
19. The method of claim 16 wherein the predetermined time period determines if the memory cell is programmed as the single level cell or the multiple level cell.
20. The method of claim 1 wherein a resistance of the magnetic tunneling junction is reduced by generating a plurality of magnetic fields along different axes above the magnetic tunneling junction.
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December 13, 2010
August 9, 2011
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