Method and apparatus for reducing memory latency in a cache coherent multi-node architecture

1. A method for reducing memory latency in a multi-node architecture, comprising: receiving a speculative memory read request from a coherence agent at a home node before results of a cache coherence protocol are determined; initiating a read to memory at the home node to complete the speculative memory read request before results of the cache coherence protocol are received by the home node; and issuing a confirm or cancel command to the home node based upon the results of the cache coherence protocol.

2. The method of claim 1 , further comprising: buffering results of the read to memory.

3. The method of claim 2 , further comprising: dropping the results of the read to memory on a buffer full condition or if a cancel command is received.

4. The method of claim 3 , further comprising: if a confirm command is received after results of the read to memory are dropped, initiating a second read to memory to complete a memory read request.

5. The method of claim 4 , further comprising: forwarding results of the second read to memory to a requesting node.

6. The method of claim 3 , further comprising: if a confirm command is received before results of the speculative read are dropped, forwarding the results of the read to memory to a requester.

7. The method of claim 6 , wherein the speculative memory read request is issued by the requesting node.

8. The method of claim 6 , further comprising: receiving the results of the read to memory at the coherence agent; and forwarding the results of the read to memory to the requesting node.