A device and method of formation are provided for a high-k gate dielectric and gate electrode. The high-k dielectric material is formed, and a silicon-rich film is formed over the high-k dielectric material. The silicon-rich film is then treated through either oxidation or nitridation to reduce the Fermi-level pinning that results from both the bonding of the high-k material to the subsequent gate conductor and also from a lack of oxygen along the interface of the high-k dielectric material and the gate conductor. A conductive material is then formed over the film through a controlled process to create the gate conductor.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for manufacturing a semiconductor device, the method comprising: providing a substrate; forming a high-k dielectric layer over the substrate; forming a silicon-rich semiconductor film over the high-k dielectric layer; treating the silicon-rich semiconductor film at least in part through the introduction of impurities that bond to the high-k dielectric layer; and forming a conductive layer over the silicon-rich semiconductor film; wherein an oxide layer is formed on the substrate prior to the forming of the high-k dielectric layer.
2. The method of claim 1 , wherein the treating the silicon-rich semiconductor film comprises at least in part oxidizing the silicon-rich semiconductor film.
3. The method of claim 1 , wherein the treating the silicon-rich semiconductor film comprises at least in part nitridizing the silicon-rich semiconductor film.
4. The method of claim 1 , wherein the forming the conductive layer over the silicon-rich semiconductor film is performed at least in part through physical vapor deposition.
5. The method of claim 1 , further comprising: removing portions of the high-k dielectric layer, the silicon-rich semiconductor film, and the conductive layer to form a gate stack, the gate stack comprising sidewalls; forming source/drain regions in the substrate on opposing sides of the gate stack; and forming spacers on the sidewalls of the gate stack.
6. The method of claim 1 , wherein the high-k dielectric layer includes a number of dangling bonds, and wherein the treating the silicon-rich semiconductor film is carried out in a manner that forms a bonding structure between the impurities and the dangling bonds.
7. The method of claim 6 , wherein the forming the conductive layer is carried out in a manner so that the bonding structure between the impurities and the dangling bonds remains intact after the conductive layer is formed.
8. A method for manufacturing a semiconductor device, the method comprising: providing a substrate; forming a layer of high-k dielectric material over the substrate; forming a semiconductor film over the layer of high-k dielectric material, the semiconductor film comprising mostly silicon; introducing impurities into the semiconductor film, at least a portion of the impurities bonding to the high-k dielectric material; and forming a layer of conductive material over the semiconductor film; wherein an oxide layer is formed on the substrate prior to the forming of the layer of high-k dielectric material.
9. The method of claim 8 , wherein the introducing the impurities is done at least in part by introducing one of oxygen and nitrogen.
10. The method of claim 8 , wherein the forming the layer of conductive material over the semiconductor film is performed at least in part through physical vapor deposition.
11. The method of claim 8 , further comprising: removing portions of the layer of high-k dielectric material, the semiconductor film, and the layer of conductive material to form a gate stack, the gate stack having sidewalls; forming source/drain regions in the substrate on opposing sides of the gate stack; and forming spacers on the sidewalls of the gate stack.
12. The method of claim 8 , wherein the high-k dielectric material comprises a silicate.
13. The method of claim 8 , wherein the high-k dielectric material comprises a metal.
14. The method of claim 8 , wherein a number of dangling bonds are located at an interface between the high-k dielectric material and the semiconductor film, and wherein the introducing the impurities is carried out so that a portion of the dangling bonds are bonded to the semiconductor film, thereby reducing the number of dangling bonds.
15. A method for manufacturing a transistor, the method comprising: providing a substrate with isolation regions formed therein; forming a layer of high-k material over the substrate, the high-k material having a plurality of dangling bonds; forming a film over the layer of high-k material, the film being a semiconductor material and comprising mostly silicon; treating the film in a manner that causes a portion of the dangling bonds to bond to the treated film; forming a gate electrode layer over the treated film; removing portions of the layer of high-k material, the treated film, and the gate electrode layer to form a gate stack; forming source/drain regions in the substrate on opposing sides of the gate stack; and forming spacers on the sidewalls of the gate stack; wherein an oxide layer is formed on the substrate prior to the forming of the layer of high-k material.
16. The method of claim 15 , wherein the treating the film comprises at least in part oxidizing the film.
17. The method of claim 15 , wherein the treating the film comprises at least in part nitridizing the film.
18. The method of claim 15 , wherein the high-k dielectric material comprises a silicate.
19. The method of 15 , wherein the forming the gate electrode is carried out in a manner so that the dangling bonds that are bonded to the treated film are not broken.
20. The method of claim 19 , wherein the forming the gate electrode is carried out using one of a physical vapor deposition process and a chemical vapor deposition process having a process temperature less than about 580 degrees Celsius.
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August 7, 2007
August 16, 2011
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