A semiconductor integrated circuit device includes: a semiconductor layer having a principal surface on which a source electrode, a drain electrode and a gate electrode are formed and having a first through hole; an insulating film formed in contact with the semiconductor layer and having a second through hole; a first interconnection formed on the semiconductor layer through the first through hole and connected to one of the source electrode, the drain electrode and the gate electrode which is exposed in the first through hole; and a second interconnection formed on the insulating film through the second through hole and connected to another of the source electrode, the drain electrode and the gate electrode which is exposed in the second through hole. The first interconnection and the second interconnection face each other and form a microstrip line.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor integrated circuit device, comprising: a first semiconductor layer having a first surface on which a source electrode, a drain electrode and a gate electrode are formed and having a first through hole; a second semiconductor layer formed on said first semiconductor layer, said first through hole extending through said second semiconductor layer, a first insulating film formed in contact with the first semiconductor layer and having a second through hole; a first metal electrode formed on a first surface of the second semiconductor layer and directly connected to the gate electrode through a metal which fills the first through hole; and a second metal electrode formed on the first insulating film and directly connected to the source electrode through a metal which fills the second through hole, wherein the first metal electrode and the second metal electrode face each other, the second metal electrode is a ground plane and the first metal electrode is a transmission line for a signal of the integrated circuit, and the first metal electrode and the second metal electrode form a microstrip line, and a high resistance region is formed in the first semiconductor layer and the second semiconductor layer between the second semiconductor layer and the first insulating film.
2. The semiconductor integrated circuit device of claim 1 , wherein the source line is made of one of gold plating, silver plating and copper plating.
3. The semiconductor integrated circuit device of claim 1 , wherein the first insulating film has a relative dielectric constant less than 3.9.
4. The semiconductor integrated circuit device of claim 3 , wherein the first insulating film is made of benzo-cyclo-butene.
5. The semiconductor integrated circuit device of claim 1 wherein the first through hole penetrates the high-resistance region.
6. The semiconductor integrated circuit device of claim 1 , wherein the first semiconductor layer is made of nitride semiconductor.
7. The semiconductor integrated circuit device of claim 6 , wherein the first semiconductor layer includes a hetero junction between aluminum gallium nitride and gallium nitride.
8. A semiconductor integrated circuit device, comprising: a first semiconductor layer having a first surface on which a source electrode, a drain electrode and a gate electrode are formed and having a first through hole; a second semiconductor layer formed on said first semiconductor layer, said first through hole extending through said second semiconductor layer; a first insulating film formed in contact with the first semiconductor layer and having a second through hole; a first metal electrode formed on a first surface of the second semiconductor layer and directly connected to the gate electrode through a metal which fills the first through hole; and a second metal electrode formed on the first insulating film and directly connected to one of the source electrode, the drain electrode or the gate electrode through a metal which fills the second hole, which is different from the source electrode, the drain electrode or the gate electrode which is connected to the first metal electrode, wherein: the first metal electrode and the second metal electrode face each other, the second metal electrode is a ground plane and the first metal electrode is a transmission line for a signal of the integrated circuit, and the first metal electrode and the second metal electrode forms a microstrip line, and a high resistance region is formed in the first semiconductor layer and the second semiconductor layer between the second semiconductor layer and the first insulating film.
9. The semiconductor integrated circuit device of claim 8 , wherein the source line is made of gold plating, silver plating and copper plating.
10. The semiconductor integrated circuit device of claim 1 , wherein the second semiconductor layer is undoped.
11. The semiconductor integrated circuit device of claim 8 , wherein the second semiconductor layer is undoped.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 16, 2006
August 23, 2011
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