A memory array is shown, including memory cells with source and drain doped regions, and global bit lines coupled to the doped regions via select transistors. The connections of the select transistors are configured such that the respective loading capacitances of two global bit lines respectively coupled to the source and the drain of a memory cell to be read do not vary with the memory cell to be read. A method of operating the memory array is also shown, including, in reading a selected memory cell, applying voltages to the gate, the drain and the source thereof respectively from a word line, a first global bit line and a neighboring second global bit line, and turning on a select transistor coupled to a third global bit line separate from the first and the second ones by at least one other global bit line.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory array, comprising: a plurality of memory cells with doped regions as sources and drains; a plurality of word lines, each coupled to gate electrodes of a row of memory cells; a plurality of local bit lines, each coupled to a column of doped regions; and a plurality of global bit lines coupled to the local bit lines via a plurality of select transistors, wherein connections of the select transistors are configured such that the source and the drain of any memory cell to be read are coupled to two neighboring global bit lines respectively, and a nearest global bit line possibly charged in reading of the memory cell is separated from the two neighboring global bit lines by at least one other global bit line.
2. The memory array of claim 1 , wherein each global bit line is coupled to two bit lines via two select transistors.
3. The memory array of claim 1 , wherein gate electrodes of the select transistors are coupled to a plurality of select lines, and the gate electrodes of the select transistors coupled to any set of a fixed number “N 1 ” (N 1 ≧4) of consecutive global bit lines are each coupled to a different select line.
4. The memory array of claim 3 , wherein the nearest global bit line is separated from the two neighboring global bit lines by a fixed number “N 2 ” (1≦N 2 <N 1 ) of other global bit line(s).
5. The memory array of claim 4 , wherein N 2 is equal to 2.
6. The memory array of claim 4 , wherein a fixed number “N 3 ” (N 3 >N 1 ) of consecutive memory cells in a row constitute a repeating unit, with N 3 doped regions thereof arranged from one side of the 1 st memory cell to between the (N 3 −1)-th memory cell and the N 3 -th memory cell; the N 3 doped regions are coupled, in a first correspondence relationship, to the N 1 global bit lines via N 3 select transistors coupled to N 3 different select lines, thus having a second correspondence relationship with the N 3 select lines; and the N 3 doped regions in any other repeating unit are coupled to another set of N 1 global bit lines in the first correspondence relationship and have the second correspondence relationship with the N 3 select lines.
7. The memory array of claim 6 , wherein N 1 =4, N 2 =2, N 3 =8, and each global bit line is coupled to two doped regions at two sides of a pair of neighboring memory cells in the repeating unit via two select transistors and two local bit lines.
8. A memory array, comprising: a plurality of memory cells with doped regions as sources and drains; a plurality of word lines, each coupled to gate electrodes of a row of memory cells; a plurality of local bit lines, each coupled to a column of doped regions; and a plurality of global bit lines coupled to the local bit lines via a plurality of select transistors controlled by a plurality of select lines, wherein among the global bit lines, a first global bit line is coupled to a first select transistor controlled by a first select line, a second global bit line neighboring to the first global bit line is coupled to a second select transistor controlled by a second select line, and a third global bit line separated from the second global bit line by at least one other global bit line is coupled to a third select transistor controlled by the first select line.
9. The memory array of claim 8 , wherein among the global bit lines, a fourth global bit line neighboring to the third global bit line is couple to a fourth select transistor controlled by the second select line.
10. The memory array of claim 8 , wherein gate electrodes of the select transistors are coupled to a plurality of select lines, and the gate electrodes of the select transistors coupled to any set of a fixed number “N 1 ” (N 1 ≧4) of consecutive global bit lines are each coupled to a different select line.
11. The memory array of claim 10 , wherein the third global bit line is separated from the second global bit lines by a fixed number “N 2 ” (1≦N 2 <N 1 ) of other global bit line(s).
12. The memory array of claim 11 , wherein N 2 is equal to 2.
13. The memory array of claim 11 , wherein a fixed number “N 3 ” (N 3 >N 1 ) of consecutive memory cells in a row constitute a repeating unit, with N 3 doped regions thereof arranged from one side of the 1 st memory cell to between the (N 3 −1)-th memory cell and the N 3 -th memory cell; the N 3 doped regions are coupled, in a first correspondence relationship, to the N 1 global bit lines via N 3 select transistors coupled to N 3 different select lines, thus having a second correspondence relationship with the N 3 select lines; and the N 3 doped regions in any other repeating unit are coupled to another set of N 1 global bit lines in the first correspondence relationship and have the second correspondence relationship with the N 3 select lines.
14. The memory array of claim 13 , wherein N 1 =4, N 2 =2, N 3 =8, and each global bit line is coupled to two doped regions at two sides of a pair of neighboring memory cells in the repeating unit via two select transistors and two local bit lines.
15. A method of operating a memory that comprises a plurality of memory cells each having a gate electrode, a source doped region and a drain doped region, a plurality of word lines each coupled to the gate electrodes of a row of memory cells, a plurality of local bit lines each coupled to a column of doped regions, a plurality of global bit lines, and a plurality of select transistors configured to connect the global bit lines to the local bit lines, the method comprising: applying a read voltage to a word line coupled to the gate electrode of a memory cell selected to be read; applying a drain voltage to the drain doped region of the selected memory cell via a first global bit line, a first select transistor that is coupled between the first global bit line and a first local bit line coupled to the drain doped region, and the first local bit line; applying a source voltage to the source doped region of the selected memory cell via a second global bit line neighboring to the first global bit line, a second select transistor that is coupled between the second global bit line and a second local bit line coupled to the source doped region, and the second local bit line; turning on a third select transistor that is coupled to a third global bit line separated from the first and the second global bit lines by at least one other global bit line; and sensing a cell current of the selected memory cell to determine a storage state of the selected memory cell.
16. The method of claim 15 , further comprising turning on a fourth select transistor that is coupled to a fourth global bit line neighboring to the third global bit line.
17. The method of claim 15 , wherein gate electrodes of the select transistors are coupled to a plurality of select lines, and the gate electrodes of the select transistors coupled to any set of a fixed number “N 1 ” (N 1 ≧4) of consecutive global bit lines are each coupled to a different select line.
18. The method of claim 17 , wherein the third global bit line is separated from the first and second global bit lines by a fixed number “N 2 ” (1≦N 2 <N 1 ) of other global bit line(s).
19. The method of claim 18 , wherein N 2 is equal to 2.
20. The method of claim 18 , wherein a fixed number “N 3 ” (N 3 >N 1 ) of consecutive memory cells in a row constitute a repeating unit, with N 3 doped regions thereof arranged from one side of the 1 st memory cell to between the (N 3 −1)-th memory cell and the N 3 -th memory cell; the N 3 doped regions are coupled, in a first correspondence relationship, to the N 1 global bit lines via N 3 select transistors coupled to N 3 different select lines, thus having a second correspondence relationship with the N 3 select lines; and the N 3 doped regions in any other repeating unit are coupled to another set of N 1 global bit lines in the first correspondence relationship and have the second correspondence relationship with the N 3 select lines.
21. The method of claim 20 , wherein N 1 =4, N 2 =2, N 3 =8, and each global bit line is coupled to two doped regions at two sides of a pair of neighboring memory cells in the repeating unit via two select transistors and two local bit lines.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 5, 2009
August 23, 2011
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