Dopant implantation method using multi-step implants

1. A method of forming a dopant implant region in a MOS transistor device, the dopant implant region having a dopant profile having a target dopant concentration, the method comprising the steps of: implanting a first concentration of dopants into a region of a substrate, said first concentration of dopants being less than said target dopant concentration; and without annealing the substrate after said implanting step, performing at least one second implanting step to implant at least one second concentration of dopants into the region of the substrate to bring the dopant concentration in the region to said target dopant concentration, wherein the implanting steps are performed in an implantation chamber of an implantation tool, the method further comprising the steps of unloading the substrate from the implantation chamber and then reloading the substrate into the implantation chamber in between said implanting steps.

2. The method of claim 1 , wherein the method includes at least three implanting steps, with the sum of respective dopant concentrations from the at least three implanting steps providing said target dopant concentration, wherein the unloading and reloading steps are performed in between successive implanting steps.

3. The method of claim 2 , wherein the method includes 3-5 of said implanting steps.

4. A method of forming a dopant implant region in a MOS transistor device, the dopant implant region having a dopant profile having a target dopant concentration, the method comprising the steps of: implanting a first concentration of dopants into a region of a substrate in an implantation chamber of an implantation tool; after said implanting step, unloading the substrate from said implantation chamber and then reloading the substrate in said implantation chamber; and after said reloading step, performing at least one second implanting step using said implantation tool to implant at least one second concentration of dopants into the region of the substrate to bring the dopant concentration in the region to said target dopant concentration.

5. The method of claim 4 , wherein the dopant profile is associated with an implant energy setting, wherein the first concentration of dopants and at least one second concentration of dopants are implanted at said implant energy setting.

6. The method of claim 4 , wherein the method includes at least three implanting steps, with the sum of respective dopant concentrations from the at least three implanting steps providing said target dopant concentration, wherein the unloading and reloading steps are performed in between successive implanting steps.

7. The method of claim 6 , wherein the method employs 3-5 implanting steps.

8. The method of claim 4 , wherein the substrate is not annealed in between implanting steps.

9. The method of claim 4 , wherein the MOS implant region is the lightly doped drain (LDD) implant portion of a source/drain implant region of the MOS transistor device, wherein the MOS transistor device has a smaller gate-to-LDD implant overlap compared to the gate-to-LDD implant overlap of a device with its LDD implant region formed using a single implanting step to implant said target dopant concentration using the same implant energy.

10. A method of forming a dopant implant region in a MOS transistor device, the dopant implant region having a dopant profile having a target dopant concentration, the method comprising the steps of: in an implantation chamber, performing multiple implanting steps, each at the same implantation energy setting and using the same dopant species, to implant dopants into a region of a semiconductor substrate until the dopant concentration of said region reaches said target dopant concentration, each implanting step implanting a respective dopant concentration that is less than said target dopant concentration; and exposing said semiconductor substrate to the ambient environment outside of the implantation chamber in between each implanting step.

11. The method of claim 10 , wherein the exposing step includes the steps of unloading the substrate from the implantation chamber and then reloading the substrate into the implantation chamber.

12. The method of claim 10 , wherein the multiple implanting steps include at least three implanting steps.

13. The method of claim 10 , wherein the substrate is not annealed in between any of said multiple implanting steps.

14. The method of claim 10 , wherein the MOS implant region is the lightly doped drain (LDD) implant portion of a source/drain implant region of the MOS transistor device, wherein the MOS transistor device has a smaller gate-to-LDD implant overlap compared to the gate-to-LDD implant overlap of a device with its LDD implant region formed using a single implanting step to implant said target dopant concentration using the same implantation energy.

15. The method of claim 14 , wherein the LDD implant portion is doped with P-type dopants.

16. The method of claim 10 , wherein the multiple implanting steps includes at least first and second implanting steps, wherein the exposing step include, in between said first and second implanting steps: unloading said semiconductor wafer from said implantation chamber; loading a second semiconductor wafer into said implantation chamber for processing; unloading said second semiconductor wafer from said implantation chamber; and reloading said first semiconductor wafer into said implantation chamber.