A memory device and programming and/or reading process is described that compensates for memory cell signal line propagation delays, such as to increase the overall threshold voltage range and non-volatile memory cell states available. Memory cell signal line propagation delay compensation can be accomplished by characterizing the memory cell signal line propagation delay, such as determining an amount of error due to the delay, and pre-compensating the programmed threshold voltage of the memory cells based on the amount of error induced by the memory cell signal line propagation delay and cell location on the selected memory cell signal line. Alternatively, memory cell signal line propagation delay can be post-compensated for, or the pre-compensation fine tuned, after sensing the threshold voltages of the selected memory cells based on the amount of error induced by the memory cell signal line propagation delay and cell location on the selected memory cell signal line. Other methods, devices, etc., are also disclosed.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of operating a memory, comprising: pre-compensating one or more threshold voltages to be programmed into one or more memory cells to compensate for memory cell signal line propagation delay of one or more memory cell signal lines coupled to the one or more memory cells; and programming the one or more pre-compensated threshold voltages into the one or more memory cells.
2. The method of claim 1 , wherein programming the one or more pre-compensated threshold voltages into the one or more memory cells comprises, programming the one or more memory cells by programming each cell to one of M+N program states where M is a number of data states that can be stored in each memory cell and N is a number of additional programming resolution states.
3. The method of claim 2 , wherein pre-compensating the one or more threshold voltages to be programmed into the one or more memory cells to compensate for memory cell signal line propagation delay of one or more memory cell signal lines coupled to the one or more memory cells, and programming the one or more memory cells by programming each cell of the one or more memory cells to one of M+N states, where M is a number of data states that can be stored in each memory cell and N is a number of additional programming resolution states comprises, pre-compensating the one or more threshold voltages to be programmed into the one or more memory cells to compensate for sensing error due to memory cell signal line propagation delay by adjusting which one of M+N program states to which the cell is to be programmed.
4. The method of claim 1 , further comprising sensing one of M+L states from the one or more memory cells, where M is a number of data states that can be stored in each memory cell and L is a number of additional sense resolution states.
5. The method of claim 1 , further comprising characterizing a memory cell signal line propagation delay of the one or more memory cell signal lines.
6. The method of claim 5 , wherein characterizing the memory cell signal line propagation delay of the one or more memory cell signal lines comprises one of determining a threshold voltage sensing error due to the memory cell signal line propagation delay of each of the one or more memory cell signal lines, and determining an RC time constant of each of the one or more memory cell signal lines.
7. The method of claim 6 , wherein characterizing the memory cell signal line propagation delay further comprises scaling the propagation delay of a particular memory cell signal line based on a particular location along the memory cell signal line.
8. A memory, comprising: a memory array; wherein the memory is adapted to pre-compensate a plurality of threshold voltages representing a plurality of states to compensate for memory cell signal line propagation delay before the plurality of threshold voltages are programmed into a plurality of selected memory cells.
9. The memory of claim 8 , wherein the memory is adapted to program the plurality of memory cells by programming each cell of the plurality of memory cells to one of M+N program states, where M is a number of data states that can be stored in each memory cell and N is a number of additional programming resolution states.
10. The memory of claim 9 , wherein the memory is adapted to pre-compensate the plurality of threshold voltages to be programmed into the plurality of memory cells to compensate for memory cell signal line propagation delay by adjusting which of the M+N program states each cell of the plurality of memory cells is to be programmed to.
11. The memory of claim 8 , wherein the memory is further adapted to perform a read operation of the plurality of selected memory cells and to post-compensate the plurality of threshold voltages representing the plurality of states to compensate for memory cell signal line propagation delay following the read operation performed on the plurality of selected memory cells.
12. The memory of claim 11 , wherein the memory is further adapted to perform a fine adjustment of the plurality of threshold voltages read from the plurality of selected memory cells wherein the fine adjustment is a function of the pre-compensation and the post-compensation performed on the plurality of threshold voltages.
13. A method of operating a memory, comprising: sensing one or more threshold voltages from one or more memory cells of the memory; and post-compensating the one or more threshold voltages sensed from the one or more memory cells to compensate for memory cell signal line propagation delays of one or more memory cell signal lines coupled to the one or more memory cells.
14. The method of claim 13 , wherein sensing one or more threshold voltages from one or more memory cells of the memory comprises, sensing one of M+L sense states of one or more memory cells, where M is a number of data states that can be stored in each memory cell and L is a number of additional sense resolution states.
15. The method of claim 14 , wherein sensing one of M+L sense states of the one or more memory cells, where M is a number of data states being stored in each memory cell and L is a number of additional sense resolution states, and post-compensating the one or more threshold voltages sensed from the one or more memory cells to compensate for sensing error due to memory cell signal line propagation delays of one or more memory cell signal lines coupled to the one or more memory cells comprises, post-compensating the one or more threshold voltages sensed from the one or more memory cells to compensate for sensing error due to memory cell signal line propagation delays of one or more memory cell signal lines coupled to the one or more memory cells by adjusting the L additional sense resolution states.
16. The method of claim 13 , further comprising programming the one or more memory cells by programming M+N program states into the one or more memory cells, where M is a number of states that can be stored in each memory cell and N is a number of additional programming resolution data states.
17. The method of claim 13 , wherein sensing one or more threshold voltages from one or more memory cells of the memory, and post-compensating the one or more threshold voltages sensed from the one or more memory cells to compensate for memory cell signal line propagation delays of one or more memory cell signal lines coupled to the one or more memory cells comprises, fine adjusting one or more pre-compensated threshold voltages sensed from one or more memory cells for current memory cell signal line delay characteristics, wherein the one or more pre-compensated threshold voltages are pre-compensated to adjust for memory cell signal line propagation delay of one or more memory cell signal lines coupled to the one or more memory cells.
18. A memory device, comprising: a memory array having a plurality of memory cells; and a control circuit; wherein the memory device is adapted to sense a plurality of threshold voltages from the plurality of memory cells; and wherein the memory device is further adapted to post-compensate the plurality of sensed threshold voltages to compensate for propagation delays of one or more memory cell signal lines coupled to the plurality of memory cells.
19. The memory device of claim 18 , wherein the memory device is further adapted to sense M+L sense states from each memory cell of the plurality of memory cells, where M is a number of data states that can be stored in each memory cell and L is a number of additional sense resolution states, and where the memory is adapted to post-compensate the plurality of threshold voltages sensed from the plurality of memory cells to compensate for memory cell signal line propagation delays of one or more memory cell signal lines coupled to the plurality of memory cells by adjusting the L additional sense resolution states.
20. The memory device of claim 18 , wherein the memory device is adapted to program each memory cell of the plurality of memory cells to one of M+N program states, where M is a number of data states that can be stored in each memory cell and N is a number of additional programming resolution states.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 31, 2008
September 20, 2011
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.