A process for manufacturing a MOS device and the MOS device manufactured thereby are disclosed. The process includes in a semiconductor layer forming a gate structure above the semiconductor layer; forming a first doped region within a first surface portion of the semiconductor layer; and irradiating the first doped region with electromagnetic radiation, to carry out annealing thereof. Prior to the irradiating step, a dielectric mirror is formed above a second surface portion of the semiconductor layer. The dielectric mirror, which may be of the Bragg-reflector type, reflects at least in part the electromagnetic radiation, and protects underlying regions from the electromagnetic radiation.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A process for manufacturing a MOS device, comprising: providing a semiconductor layer; forming a gate structure above said semiconductor layer; forming a first doped region within a first surface portion of said semiconductor layer; forming a dielectric mirror above a second surface portion of said semiconductor layer; and irradiating said first doped region with electromagnetic radiation to carry out annealing thereof; wherein said forming the dielectric mirror is prior to said irradiating and wherein said irradiating of the first doped region further comprises said dielectric mirror being configured to reflect at least in part said electromagnetic radiation.
2. The process according to claim 1 , wherein forming a dielectric mirror comprises forming said dielectric mirror above said gate structure, said dielectric mirror being configured to shield said gate structure from said electromagnetic radiation.
3. The process according to claim 2 , wherein forming a first doped region comprises carrying out an introduction of dopant species in a way aligned with respect to said gate structure and to said dielectric mirror, in order to form said first doped region in a position adjacent to, and partially underneath, said gate structure.
4. The process according to claim 1 , wherein forming a dielectric mirror comprises forming said dielectric mirror at said second surface portion of said semiconductor layer, said dielectric mirror being configured to protect said second surface portion from said electromagnetic radiation; and wherein the step of forming a gate structure is performed subsequent to said irradiating step.
5. The process according to claim 4 , wherein forming a first doped region comprises forming said first doped region in a position at a lateral distance from said dielectric mirror.
6. The process according to claim 5 , wherein forming said first doped region in a position at a lateral distance from said dielectric mirror comprises: forming second spacers at the sides of said dielectric mirror; forming a second doped region within said semiconductor layer, at the sides of, and partially underneath, said second spacers; carrying out a thermal treatment of said second doped region, which causes a lateral diffusion of said second doped region for a lateral extension, said second spacers having a first thickness at the base greater than said lateral extension; and carrying out an introduction of dopant species in a way aligned with respect to said second spacers so as to form said first doped region within said second doped region.
7. The process according to claim 5 , wherein forming a dielectric mirror comprises forming a temporary dielectric mirror in an area corresponding to said second surface portion of said semiconductor layer, and reducing said temporary dielectric mirror so as to form said dielectric mirror; and wherein forming said doped region in a position at a lateral distance from said dielectric mirror comprises: forming a second doped region within said semiconductor layer, at the sides of, and partially underneath, said temporary dielectric mirror; carrying out a thermal treatment of said second doped region, which causes a lateral diffusion of said second doped region for a lateral extension; and carrying out an introduction of dopant species in a way aligned with respect to said temporary dielectric mirror to form said first doped region within said second doped region, reducing said temporary dielectric mirror comprising reducing a main dimension of said temporary dielectric mirror by an amount of not less than said lateral extension.
8. A process for manufacturing a MOS device, comprising: providing a semiconductor layer; forming a gate structure above said semiconductor layer; forming a first doped region within a first surface portion of said semiconductor layer; forming a dielectric mirror above a second surface portion of said semiconductor layer; and irradiating said first doped region with electromagnetic radiation to carry out annealing thereof; wherein said forming the dielectric mirror is prior to said irradiating and wherein said irradiating of the first doped region further comprises, said dielectric mirror being configured to reflect at least in part said electromagnetic radiation; and wherein forming a dielectric mirror comprises: forming a plurality of pairs of a first mirror layer and a second mirror layer, set on top of one another, said first mirror layer and said second mirror layer having, respectively, a first refractive index and a second refractive index that are different from one another; and etching said first mirror layer and said second mirror layer so as to form said dielectric mirror.
9. The process according to claim 8 , wherein said dielectric mirror comprises a Bragg reflector, and said electromagnetic radiation has a given wavelength; a first optical thickness of said first mirror layer and of said second mirror layer being equal to a multiple of a quarter of said given wavelength.
10. A process for manufacturing a MOS device, comprising: providing a semiconductor layer; forming a gate structure above said semiconductor layer; forming a first doped region within a first surface portion of said semiconductor layer; forming a dielectric mirror above a second surface portion of said semiconductor layer; and irradiating said first doped region with electromagnetic radiation to carry out annealing thereof; wherein said forming the dielectric mirror is prior to said irradiating and wherein said irradiating of the first doped region further comprises, said dielectric mirror being configured to reflect at least in part said electromagnetic radiation; and further comprising, prior to said irradiating step, forming a buffer region on said dielectric mirror, said buffer region having optical characteristics such as not to reduce a reflectivity of said dielectric mirror.
11. The process according to claim 10 , wherein said electromagnetic radiation has a given wavelength; further comprising, prior to said irradiating step, forming a capping region on said buffer layer and above said first surface portion of said semiconductor layer, said capping region having optical characteristics such as to improve an energy coupling with said electromagnetic radiation, and such as not to reduce said reflectivity of said dielectric mirror; in particular, said capping region comprising a dielectric material and having a second optical thickness, and said buffer region having a third optical thickness given by the difference between a multiple of one half of said given wavelength, and said second optical thickness.
12. A process for manufacturing a MOS device, comprising: providing a semiconductor layer; forming a gate structure above said semiconductor layer; forming a first doped region within a first surface portion of said semiconductor layer; forming a dielectric mirror above a second surface portion of said semiconductor layer; and irradiating said first doped region with electromagnetic radiation to carry out annealing thereof; wherein said forming the dielectric mirror is prior to said irradiating and wherein said irradiating of the first doped region further comprises, said dielectric mirror being configured to reflect at least in part said electromagnetic radiation; and wherein forming a dielectric mirror comprises forming said dielectric mirror above said gate structure, said dielectric mirror being configured to shield said gate structure from said electromagnetic radiation; the process further comprising forming a first conductive region set between said gate structure and said dielectric mirror; said first conductive region comprising, in particular, a metal or a metallic silicide, chosen preferably in the group comprising: W, Mo, Ti, Ta, CoSi x , PtSi x , TiSi x , WSi x .
13. The process according to claim 12 , further comprising, prior to said irradiating step, forming a capping region on said dielectric mirror; and wherein forming a gate structure comprises: forming a first gate dielectric layer on said semiconductor layer; forming a first gate conductive layer on said first gate dielectric layer; and selectively removing portions of said first gate conductive layer, thereby forming a first gate electrode; further comprising oxidizing side walls of said first gate electrode prior to forming said capping region.
14. The process according to claim 12 , wherein forming a dielectric mirror comprises: forming a plurality of pairs of a first mirror layer and a second mirror layer, set on top of one another, at least one between said first mirror layer and said second mirror layer comprising an insulating material; further comprising: forming a second doped region within said semiconductor layer, at the sides of, and partially underneath, said gate structure, forming a first doped region comprising forming said first doped region within said second doped region; forming a conductive layer above said dielectric mirror and said semiconductor layer, said conductive layer configured to contact said first doped region and said second doped region.
15. The process according to claim 14 , further comprising forming first spacers at the sides of said gate structure and said dielectric mirror prior to forming said conductive layer; and wherein forming a first doped region comprises defining a lateral extension of said first doped region, said lateral extension being smaller than a main dimension of said second doped region.
16. The process according to claim 14 , further comprising forming first spacers at the sides of said gate structure and of said dielectric mirror prior to forming said conductive layer; and etching said semiconductor layer to dig a trench having a depth greater than a depth of said first doped region, in such a manner as to reach said second doped region; forming a second conductive layer comprising filling said trench.
17. A process for manufacturing a MOS device, comprising: providing a semiconductor layer; forming a gate structure above said semiconductor layer; forming a first doped region within a first surface portion of said semiconductor layer; forming a dielectric mirror above a second surface portion of said semiconductor layer; and irradiating said first doped region with electromagnetic radiation to carry out annealing thereof; wherein said forming the dielectric mirror is prior to said irradiating and wherein said irradiating of the first doped region further comprises, said dielectric mirror being configured to reflect at least in part said electromagnetic radiation; wherein forming a dielectric mirror comprises forming said dielectric mirror at said second surface portion of said semiconductor layer, said dielectric mirror being configured to protect said second surface portion from said electromagnetic radiation; and wherein the step of forming a gate structure is performed subsequent to said irradiating step; wherein forming a first doped region comprises forming said first doped region in a position at a lateral distance from said dielectric mirror; and wherein forming a dielectric mirror comprises forming a plurality of pairs of a first mirror layer and a second mirror layer, set on top of one another, at least one between said first mirror layer and said second mirror layer comprising an insulating material; and wherein forming a gate structure comprises: forming a second gate dielectric layer on said semiconductor layer, in a position adjacent to said dielectric mirror; forming a second gate conductive layer on said second gate dielectric layer, and above, and surrounding, said dielectric mirror; and selectively removing portions of said second gate conductive layer, thereby forming a second gate electrode.
18. The process according to claim 17 , further comprising, prior to forming said dielectric mirror, forming an end point layer, including dielectric material, on said semiconductor layer; and, prior to forming a gate structure, removing said end point layer from the areas not covered by said dielectric mirror.
19. The process according to claim 17 , wherein selectively removing comprises one between: selectively removing portions of said second gate conductive layer in such a manner as to leave first gate-electrode portions laterally in contact with said dielectric mirror, said first gate-electrode portions having a second thickness at the base not less than said first thickness at the base of said second spacers; or selectively removing portions of said second gate conductive layer in such a manner as to leave, in addition to said first gate-electrode portions, second gate-electrode portions arranged on said dielectric mirror; or selectively removing portions of said second gate conductive layer so as to leave a single gate portion arranged laterally in contact with, and on, said dielectric mirror, and extending in part above said first doped region and said second doped region.
20. A method of forming a device in a semiconductor layer; forming a gate structure over the semiconductor layer; forming a first doped region within a first portion of the semiconductor layer; forming a dielectric mirror over a second portion of the substrate adjacent the first portion; and irradiating the first doped region with electromagnetic radiation to anneal the first doped region after the forming of the dielectric mirror such that at least some electromagnetic radiation is reflected by the dielectric mirror.
21. The method of claim 20 further comprising forming a gate structure over the second portion of the semiconductor layer, the gate structure being formed between the semiconductor layer and the dielectric mirror.
22. The method of claim 20 further comprising forming a gate structure over a third portion of the semiconductor layer, the third portion being positioned between the first and second portions and corresponding to a channel region of the device, and the gate structure being formed adjoining a sidewall portion of the dielectric mirror.
23. The method of claim 20 further comprising: forming the dielectric mirror extending over a third portion of the semiconductor layer, the third portion being positioned between the first and second portions; removing portions of the gate structure over the third portion of the semiconductor layer; and forming a gate structure over the third portion of the semiconductor layer.
24. The method of claim 20 wherein the device comprises a MOS device and the first doped region comprises a source or drain region of the device.
25. A method of forming a device in a semiconductor layer; forming a gate structure over the semiconductor layer; forming a first doped region within a first portion of the semiconductor layer; forming a dielectric mirror over a second portion of the substrate adjacent the first portion; and irradiating the first doped region with electromagnetic radiation to anneal the first doped region after the forming of the dielectric mirror such that at least some electromagnetic radiation is reflected by the dielectric mirror; wherein the dielectric mirror comprises a Bragg reflector adapted to reflect the electromagnetic radiation.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 22, 2006
October 4, 2011
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.