A display device of high definition, multiple colors and low power consumption includes a display panel having a pixel section in which pixels are arrayed in the form of a matrix at the cross points of a plurality of data lines and a plurality of scanning lines, a scanning circuit for applying voltage sequentially to the plurality of scanning lines, and a data-line driver, which receives display data supplied by a host device, for applying signals corresponding to the display data to the plurality of data lines. Provided external to the display panel is a controller IC having a display memory for storing display data corresponding to the pixel section, an output buffer for reading data out of the display memory and outputting this data to the display panel, and a controller for controlling the display memory and output buffer and communication with the host device. The display panel is provided with a digital/analog converter, which forms part of the data-line driver, for converting display data represented by a digital signal to an analog signal. The width of a bus for data transfer between the controller IC and data-line driver of the display panel is such that data of a greater number of bits is transferred in parallel by a single transfer than is transferred by the bus between the controller and the host device. This allows the operating frequency of the data-line driver to be reduced.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A display device comprising: an array unit in which a plurality of devices to be driven are arrayed in a form of a matrix; and a serial/parallel converting circuit unit having more than one bit input for performing parallel processing of data for driving said devices to be driven, said serial/parallel converting circuit unit comprising of a plurality of serial/parallel converting circuits, each having one bit input; wherein a group of output nodes of said serial/parallel converting circuit unit are arranged along and aligned within a length of a first side of said array unit of devices to be driven, said devices adapted to be driven by a group of electric signals supplied through said first side of said array unit of device to be driven, based on a group of signals out of said group of output nodes; wherein wirings for transferring a display signal do not intersect wirings for displaying another display signal in a section of said serial/parallel converting circuit unit.
2. A semiconductor device comprising: an array unit in which a plurality of devices to be driven are arrayed in a form of a matrix; and a serial/parallel converting circuit unit having more than one bit input for performing parallel processing of data for driving said devices to be driven, said serial/parallel converting circuit unit comprising of a plurality of serial/parallel converting circuits, each having one bit input; wherein a group of output nodes of said serial/parallel converting circuit unit are arranged along and aligned within a length of a first side of said array unit of devices to be driven, the array unit of devices are adapted to be driven by a group of electric signals supplied through said first side, based on a group of signals out of said group of output nodes, wherein wirings for transferring a data signal do not intersect wirings for displaying another data signal in a section of said serial/parallel converting circuit unit.
5. A semiconductor device comprising: an array unit in which a plurality of devices to be driven are arrayed in a form of a matrix; and a serial/parallel converting circuit unit having more than 1 bit input for performing parallel processing of data for driving said device to be driven, said serial/parallel converting circuit unit comprised of a plurality of serial/parallel converting circuits, each having one bit input; wherein a group of output nodes of said serial/parallel converting circuit unit are arranged along and aligned within a length of a first side of said array unit of devices to be driven which are adapted to be driven by a group of electric signals supplied through said first side of said array unit of device to be driven based on a group of signals output by said group of output nodes.
6. The semiconductor device according to claim 5 , wherein at least two number of serial/parallel converting circuits in said serial/parallel converting circuit unit are driven synchronously by a control line connected in common to said two number of serial/parallel converting circuits.
7. A semiconductor device comprising: an array unit in which a plurality of devices to be driven are arrayed in a form of a matrix; a driver circuit for writing an electric signal into said devices to be driven; and a serial/parallel converting circuit unit having more than 1 bit input for performing parallel processing of data, a group of output nodes for outputting a signal obtained on serial/parallel converting data supplied to a first input node of said serial/parallel converting circuit unit, and a group of output nodes for outputting a signal obtained on serial/parallel converting data supplied to a second input node, adjacent to said first input node of said serial/parallel converting circuit unit being arranged adjacent; wherein said group of output nodes of said serial/parallel converting circuit unit are arranged along and aligned within a length of a first side of said array unit of devices to be driven which are adapted to be driven by a group of electric signals supplied through said first side of said array unit based on a group signals output by said group output nodes.
8. A semiconductor device comprising: an array unit in which a plurality of devices to be driven are arrayed in the form of a matrix; a driver circuit for writing an electric signal into said devices to be driven; and a serial/parallel converting circuit unit having more than 1 bit input for performing parallel processing of data, said serial/parallel converting circuit unit being arranged with a layout pattern having substantially a form of a rectangle, a group of input nodes of said serial/parallel converting circuit unit being provided on one of longer sides of said rectangle and a group of output nodes of said serial/parallel converting circuit unit being provided on another longer side of said rectangle; and said serial/parallel converting circuit being formed as an integrated circuit laid-out on a substrate; wherein said group of output nodes are arranged along and aligned within a length of a first side of said array unit of devices to be driven, and said devices to be driven are adapted to be driven by a group of electric signals supplied through said first side of said array unit based on a group signals output by said group output nodes.
9. The display device according to claim 3 comprising: a display device substrate including pixels arrayed in the form of a matrix in the vicinity of intersections between a plurality of data lines and a plurality of scanning lines, wherein said display device substrate is equipped with said circuit for subjecting display data to a phase expansion.
10. The display device according to claim 9 further comprising: a controller IC provided externally of said display device substrate; and a data-line driver circuit that is formed on said display device substrate and applies signals corresponding to the display data to said plurality of data lines; wherein said controller IC includes a display memory that stores display data, an output buffer that reads data out of said display memory and outputs the data to said display device substrate, and a controller that controls said display memory and said display device; and wherein a bus for data transfer between said controller IC and said display device substrate has a width such that data of a greater number of bits is transferred in parallel per one transfer than is transferred by a bus between said controller IC and said host device.
11. A display device comprising a display device substrate and a controller IC provided externally of said display device substrate; wherein said display device substrate comprises said semiconductor device according to claim 5 provided that said array unit comprises a plurality of pixels arrayed in the form of a matrix in the vicinity of intersections between a plurality of data lines and a plurality of scanning lines; a data-line driver circuit applies signals corresponding to the display data to said plurality of data lines is formed on said display device substrate; said controller IC has a display memory that stores display data, an output buffer that reads data out of said display memory and outputs the data to said display device substrate, and a controller that controls said display memory and said display device; a bus for data transfer between said controller IC and said display device substrate has a width such that data of a greater number of bits is transferred in parallel by one transfer than is transferred by a bus between said controller and a host device of higher ordinate.
12. A display device comprising a display device substrate and a controller IC provided externally of said display device substrate, wherein said display device substrate comprises said semiconductor device according to claim 7 provided that said array unit comprises a plurality of pixels arrayed in the form of a matrix in the vicinity of intersections between a plurality of data lines and a plurality of scanning lines, a data-line driver circuit that applies signals corresponding to the display data to said plurality of data lines is formed on said display device substrate; said controller IC comprises a display memory that stores display data, an output buffer that reads data out of said display memory and outputs the data to said display device substrate, and a controller that controls said display memory and said display device; a bus for data transfer between said controller IC and said display device substrate has a width such that data of a greater number of bits is transferred in parallel per one transfer than is transferred by a bus between said controller and a host device of a higher ordinate.
13. A display device comprising a display device substrate and a controller IC provided externally of said display device substrate; wherein said display device substrate comprises said semiconductor device according to claim 8 provided that said array unit comprises a plurality pixels arrayed in the form of a matrix in the vicinity of intersections between a plurality of data lines and a plurality of scanning lines; a data-line driver circuit that applies signals corresponding to the display data to said plurality of data lines is formed on said display device substrate; said controller IC comprises a display memory that stores display data, an output buffer that reads data out of said display memory and outputs the data to said display device substrate, and a controller that controls said display memory and said display device; a bus for data transfer between said controller IC and said display device substrate has a width such that data of a greater number of bits is transferred in parallel per one a single transfer than is transferred by a bus between said controller and a host device.
14. The semiconductor device according to claim 5 , wherein the group of output nodes are arranged along only the first side of said array unit of devices to be driven.
15. The semiconductor device according to claim 7 , wherein the group of output nodes are arranged along only the first side of said array unit of devices to be driven.
16. The semiconductor device according to claim 8 , wherein the group of output nodes are arranged along only the first side of said array unit of devices to be driven.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 10, 2006
October 11, 2011
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