A semiconductor storage device comprises: a sense amplifier circuit; a first data retaining circuit and a second data retaining circuit configured to retain data and threshold voltage information, the second data retaining circuit output the data and the threshold voltage information to the outside; and a control circuit configured to control operation. The sense amplifier circuit is configured to perform a data-read operation and a threshold-voltage-information read operation at the same time. The control circuit is configured to control read operations so that either one of the data or the threshold voltage information for which a read operation is finished earlier is output from the second data retaining circuit, and the other one of the data or the threshold voltage information for which a read operation is not finished yet is read from a memory cell array and retained in the first data retaining circuit.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor storage device comprising: a memory cell array having a plurality of memory cells, each of the memory cells capable of storing multiple bits of information allocated to a plurality of threshold voltage distributions; a sense amplifier circuit configured to read data stored in the memory cell as well as threshold voltage information indicative of at which position a threshold voltage of the memory cell is positioned in one of the plurality of threshold voltage distributions; a first data retaining circuit configured to retain the data and the threshold voltage information read from the memory cell; a second data retaining circuit configured to retain the data and the threshold voltage information read from the memory cell, and output the data and the threshold voltage information to an outside circuit; and a control circuit configured to control read, write, and erase operations on the memory cell array, the sense amplifier circuit being configured to perform a data-read operation and a threshold-voltage-information read operation at the same time by a series of voltage application operations to a word line connected to the memory cell, the control circuit being configured to control read operations so that either one of the data or the threshold voltage information for which a read operation is finished earlier is output from the second data retaining circuit, and the other one of the data or the threshold voltage information for which a read operation is not finished yet is read from the memory cell array and retained in the first data retaining circuit.
2. The semiconductor storage device according to claim 1 , wherein the sense amplifier circuit is configured to perform the data-read operation and the threshold-voltage-information read operation at the same time by sequentially increasing values of voltage applied to the word line.
3. The semiconductor storage device according to claim 1 , wherein the sense amplifier circuit is configured to perform the threshold-voltage-information read operation by applying respective intermediate voltages between both ends of the plurality of threshold voltage distributions.
4. The semiconductor storage device according to claim 1 , wherein the sense amplifier circuit is configured to perform the threshold-voltage-information read operation by applying a voltage that is decremented from an upper limit of each of the plurality of threshold voltage distributions by a voltage with one-fourth of a width of each of the threshold voltage distributions, and a voltage that is incremented from a lower limit of each of the threshold voltage distributions by a voltage with one-fourth of the width of each of the threshold voltage distributions.
5. The semiconductor storage device according to claim 1 , further comprising an ECC circuit configured to correct data read from the memory cell array based on the threshold voltage information and redundant data.
6. The semiconductor storage device according to claim 1 , wherein the control circuit is configured to control read operations so that a part of the data or the threshold voltage information is retained in the second data retaining circuit and output the data or the threshold voltage information to the outside when performing the data-read operation and the threshold-voltage-information read operation.
7. The semiconductor storage device according to claim 1 , further comprising an arithmetic circuit configured to perform a logical operation between data detected by the sense amplifier circuit and data retained by the first data retaining circuit or the second data retaining circuit, and transfer the operation result to the first data retaining circuit or the second data retaining circuit.
8. The semiconductor storage device according to claim 7 , wherein a plurality of the first data retaining circuits are provided, and the arithmetic circuit is configured to perform the logical operation on data retained by the plurality of the first data retaining circuits.
9. A semiconductor storage device comprising: a memory cell array having a plurality of memory cells, each of the memory cells capable of storing multiple bits of information allocated to a plurality of threshold voltage distributions; a sense amplifier circuit configured to read data stored in the memory cell as well as threshold voltage information indicative of at which position a threshold voltage of the memory cell is positioned in one of the plurality of threshold voltage distributions; a first data retaining circuit configured to retain the data and the threshold voltage information read from the memory cell; a second data retaining circuit configured to retain the data and the threshold voltage information read from the memory cell, and output the data and the threshold voltage information to an outside circuit; and a control circuit configured to control read, write, and erase operations on the memory cell array, the memory cell storing multiple pages of information corresponding to the multiple bits of information, the sense amplifier circuit being configured to perform a data-read operation on a page-by-page basis by applying a voltage to a word line connected to the memory cell, and the control circuit being configured to control a read operation so that the data is output from the second data retaining circuit, and the threshold voltage information is read from the memory cell array and retained in the first data retaining circuit.
10. The semiconductor storage device according to claim 9 , wherein the sense amplifier circuit is configured to perform a threshold-voltage-information read operation by applying respective intermediate voltages between both ends of the plurality of threshold voltage distributions.
11. The semiconductor storage device according to claim 9 , wherein the sense amplifier circuit is configured to perform a threshold-voltage-information read operation by applying a voltage that is decremented from an upper limit of each of the plurality of threshold voltage distributions by a voltage with one-fourth of a width of each of the threshold voltage distributions, and a voltage that is incremented from a lower limit of each of the threshold voltage distributions by a voltage with one-fourth of the width of each of the threshold voltage distributions.
12. The semiconductor storage device according to claim 9 , further comprising an ECC circuit configured to correct data read from the memory cell array based on the threshold voltage information and redundant data.
13. The semiconductor storage device according to claim 9 , wherein the control circuit is configured to control the read operation so that a part of the data is retained in the second data retaining circuit and output the data and the threshold voltage information to the outside circuit when performing the data-read operation.
14. The semiconductor storage device according to claim 9 , further comprising an arithmetic circuit configured to perform a logical operation between data detected by the sense amplifier circuit and data retained by the first data retaining circuit or the second data retaining circuit, and transfer the operation result to the first data retaining circuit or the second data retaining circuit.
15. The semiconductor storage device according to claim 14 , wherein a plurality of the first data retaining circuits are provided, and the arithmetic circuit is configured to perform logical operation on data retained by the plurality of the first data retaining circuits.
16. A semiconductor storage device comprising: a memory cell array having a plurality of memory cells, each of the memory cells capable of storing multiple bits of information allocated to a plurality of threshold voltage distributions; a sense amplifier circuit configured to read data stored in the memory cell as well as threshold voltage information indicative of where a threshold voltage of the memory cell is positioned in one of the plurality of threshold voltage distributions; a first data retaining circuit configured to retain the data and the threshold voltage information read from the memory cell; a second data retaining circuit configured to retain the data and the threshold voltage information read from the memory cell, and output the data and the threshold voltage information to an outside circuit; and a control circuit configured to control read, write, and erase operations on the memory cell array, the sense amplifier circuit being configured to perform a data-read operation by applying a voltage to a word line connected to the memory cell, and the control circuit being configured to control a read operation so that the data is output from the second data retaining circuit, and threshold voltage information is read from the memory cell array and retained in the first data retaining circuit.
17. The semiconductor storage device according to claim 16 , wherein the sense amplifier circuit is configured to perform a threshold-voltage-information read operation by applying respective intermediate voltages between both ends of the plurality of threshold voltage distributions.
18. The semiconductor storage device according to claim 16 , wherein the sense amplifier circuit is configured to perform a threshold-voltage-information read operation by applying a voltage that is decremented from an upper limit of each of the plurality of threshold voltage distributions by a voltage with one-fourth of a width of each of the threshold voltage distributions, and a voltage that is incremented from a lower limit of each of the threshold voltage distributions by a voltage with one-fourth of width of each of the threshold voltage distributions.
19. The semiconductor storage device according to claim 16 , further comprising an ECC circuit configured to correct data read from the memory cell array based on the threshold voltage information and redundant data.
20. The semiconductor storage device according to claim 16 , further comprising an arithmetic circuit configured to perform a logical operation between data detected by the sense amplifier circuit and data retained by the first data retaining circuit or the second data retaining circuit, and transfer the operation result to the first data retaining circuit or the second data retaining circuit.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 22, 2009
October 11, 2011
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