A method of this invention involves capturing an image of an outer periphery of a semiconductor wafer, by use of a CCD camera, performing image analysis on data about the captured image, detecting defects such as chips and cracks on the outer periphery of the semiconductor wafer, storing positions of the respective defects, calculating a clearance between the adjacent defects from information about the stored positions, comparing the calculated clearances with a preset width of a separation tape, and obtaining the clearance larger than the width of the separation tape, by arithmetic processing. If some of the clearances are larger than the width of the separation tape, this method also involves setting an appropriate one of the clearance as a position where the separation tape is joined, performing alignment on the semiconductor wafer, joining the separation tape to a protective tape joined to a surface of the semiconductor wafer, and separating the protective tape together with the separation tape from the surface of the semiconductor wafer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for joining, to a protective tape joined to a surface of a semiconductor wafer, a separation tape having a width narrower than a diameter of the semiconductor wafer to separate the protective tape together with the separation tape from the surface of the semiconductor wafer, the method comprising: detecting defects on an outer periphery of a semiconductor wafer, and storing positions of the respective defects; calculating a clearance between the adjacent defects from information about the stored positions, comparing the calculated clearances with a width of a separation tape, and obtaining the clearance larger than the width of the separation tape; and setting the clearance as a position for starting to join the separation tape, and joining the separation tape to the clearance and separating the separation tape from the clearance.
2. The method according to claim 1 , wherein the joining of the separation tape is started at a largest portion in the calculated clearance.
3. The method according to claim 1 , wherein the defect is detected by: acquiring information about a wafer outer peripheral area covering an alignment mark formed on the semiconductor wafer, by use of a sensor; and converting a portion to be assumed as the defect into a coordinate, and matching the coordinate to reference coordinate information about a non-defective semiconductor wafer having only an alignment mark formed thereon to obtain a portion excluding the alignment mark.
4. The method according to claim 3 , wherein when some of the clearances are larger than the width of the separation tape, a largest one of the clearances is set as a separation start position.
5. The method according to claim 4 , wherein the largest clearance is obtained by: converting the defects on the outer periphery of the semiconductor wafer into coordinates, respectively, and obtaining a linear distance between the coordinates of the adjacent defects; comparing the linear distances with the width of the separation tape to extract the linear distance larger than the width of the separation tape, and obtaining a midpoint coordinate on a line corresponding to the linear distance; obtaining a center line connecting between the midpoint coordinate and a center coordinate of the semiconductor wafer; obtaining linear distances between the center line and all the coordinates of each defect, the linear distances being perpendicular to the center line; and obtaining a portion where all the distances between the coordinates of the defects opposed to each other with the center line located therebetween are larger than the width of the separation tape, and setting the portion as the separation start position.
6. The method according to claim 1 , wherein the defect is detected by: acquiring information about the entire semiconductor wafer, by use of a sensor; and converting a portion to be assumed as the defect into a coordinate, and matching the coordinate to reference coordinate information about a non-defective semiconductor wafer having only an alignment mark formed thereon to obtain a portion excluding the alignment mark.
7. The method according to claim 6 , wherein when some of the clearances are larger than the width of the separation tape, a largest one of the clearances is set as a separation start position.
8. The method according to claim 7 , wherein the largest clearance is obtained by: converting the defects on the outer periphery of the semiconductor wafer into coordinates, respectively, and obtaining a linear distance between the coordinates of the adjacent defects; comparing the linear distances with the width of the separation tape to extract the linear distance larger than the width of the separation tape, and obtaining a midpoint coordinate on a line corresponding to the linear distance; obtaining a center line connecting between the midpoint coordinate and a center coordinate of the semiconductor wafer; obtaining linear distances between the center line and all the coordinates of each defect, the linear distances being perpendicular to the center line; and obtaining a portion where all the distances between the coordinates of the defects opposed to each other with the center line located therebetween are larger than the width of the separation tape, and setting the portion as the separation start position.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 3, 2009
October 18, 2011
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