One embodiment of the invention relates to a method of manufacturing a light emitting diode. The method includes forming an insulating layer on an area, not covered by a seed layer, of at least one of a p-type semiconductor layer and an n-type semiconductor layer, wherein the impurity concentration varies on the surface of the area; and immersing at least part of the seed layer into an electrolyte having metal ions which tend to reduce and deposit on the seed layer under no bias voltage.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of manufacturing a light-emitting structure, comprising: providing a substrate; forming a semiconductor multilayer on the substrate, the semiconductor multilayer comprising a p-type semiconductor layer, an n-type semiconductor layer, and a light-emitting region between the p-type semiconductor layer and the n-type semiconductor layer, wherein the p-type semiconductor layer or the n-type semiconductor layer has a varying impurity concentration therein; forming a pre-covering layer on only a portion of the p-type semiconductor layer and the n-type semiconductor layer; forming an insulating layer on the p-type semiconductor layer and the n-type semiconductor layer and exposing a part of the pre-covering layer; and electroless plating an electrode layer by immersing the exposed pre-covering layer into an electrolyte having metal ions which reduce and deposit the electrode layer on the exposed pre-covering layer; wherein the pre-covering layer is a seed layer for electroless plating the electrode layer.
2. The method of claim 1 , further comprising: removing the insulating layer.
3. The method of claim 1 , further comprising: forming a conductive layer between the pre-covering layer and at least one of the p-type semiconductor layer and the n-type semiconductor layer.
4. The method of claim 1 , further comprising: forming a transparent conductive layer between the pre-covering layer and at least one of the p-type semiconductor layer and the n-type semiconductor layer.
5. The method of claim 1 , wherein the insulating layer is formed on the same side of the p-type semiconductor layer and the n-type semiconductor layer.
6. The method of claim 1 , further comprising: separating the semiconductor multilayer to form at least one light-emitting diode chip.
7. The method of claim 1 , further comprising: forming a bond pad on a side opposite to the pre-covering layer.
8. The method of claim 1 , wherein the electrolyte is selected from a group consisting of gold sodium sulfide, copper sulfate, and nickel sulfate.
9. The method of claim 1 , wherein a material of the pre-covering layer is selected from a group consisting of gold, copper, and nickel.
10. The method of claim 1 , wherein a material of the conductive layer is selected from a group consisting of chromium, platinum, nickel, and germanium.
11. The method of claim 1 , wherein the pre-covering layer has a thickness between 100 Ř5000 Å.
12. The method of claim 1 , wherein the insulating layer has a thickness between 100 Ř17 μm.
13. The method of claim 3 , wherein the conductive layer has a thickness between 100 Ř1000 Å.
14. The method of claim 4 , wherein a material of the transparent conductive layer is selected from a group consisting of ITO, CTO, IZO, AZO, and transparent conductive metal.
15. The method of manufacturing a light-emitting structure of claim 1 , further comprising reducing and depositing the metal ions on the pre-covering layer of uniform thickness.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 7, 2007
October 18, 2011
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